From: Eugene Leitl (Eugene.Leitl@lrz.uni-muenchen.de)
Date: Fri Aug 31 2001 - 01:55:09 MDT
On Thu, 30 Aug 2001, Robert J. Bradbury wrote:
> A decade ago nobody realized that it is the CPU-to-memory bandwidth
> that is the big problem. Now IBM is building an entire architecture
Nobody of the vendors, you mean. The user base groked it early enough.
> designed to avoid that. It isn't clear to me whether Intel is
> following suit, but they are investing huge amounts in chip
> architectures (multi-level caches, multi-ALUs, etc.) that seem to be
> oriented towards avoiding solving that problem. Further there are no
> indications that they are trying to integrate the memory with the
> logic on a single chip (as IBM is doing).
Current CPUs are absolutely ridiculous. About 90% of the die is used up to
deal with condequences arising from having used up 90% of the die, so you
can't put memory on die.
> IBM in contrast seems willing to take the hit and develop a process
> that supports memory and logic on the same chip. Big difference
> in corporate strategies.
Embedded DRAM has been the holy grail for decades. Now IBM just went
ahead, and did it. For that, one could almost forgive them the PC
architecture. Almost.
> INTEL seems to be planning for the 5 year time frame while IBM
> seems to be planning for the 10 year time frame.
If it was in my power, I would prefer using designs derived from
Making them wider, and integrating them with embedded DRAM (or FERAM, or
MRAM) would seem to make for very interesting designs.
-- Eugen* Leitl leitl
______________________________________________________________
ICBMTO : N48 10'07'' E011 33'53'' http://www.lrz.de/~ui22204
57F9CFD3: ED90 0433 EB74 E4A9 537F CFF5 86E7 629B 57F9 CFD3
This archive was generated by hypermail 2.1.5 : Sat Nov 02 2002 - 08:10:17 MST