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| author | John Thornton <jthornton@gnipsel.com> | 2011-12-17 11:56:13 -0600 |
|---|---|---|
| committer | John Thornton <jthornton@gnipsel.com> | 2011-12-17 11:56:13 -0600 |
| commit | ae545df0c54c094a65344e1f5d77673a99dc5702 (patch) | |
| tree | ce134b0dc618a36ce8e320b3088698ea44c16996 | |
| parent | be20fdb57ca56ead13932c1381fc75a34f72e068 (diff) | |
| download | linuxcnc-ae545df0c54c094a65344e1f5d77673a99dc5702.tar.gz linuxcnc-ae545df0c54c094a65344e1f5d77673a99dc5702.zip | |
Docs: markup fixes and latexmath fix
Signed-off-by: John Thornton <jthornton@gnipsel.com>
| -rw-r--r-- | docs/src/drivers/images/pico-ppmc-math.png | bin | 0 -> 4020 bytes | |||
| -rw-r--r-- | docs/src/drivers/pico_ppmc.txt | 112 | ||||
| -rw-r--r-- | docs/src/drivers/pico_ppmc_de.txt | 129 | ||||
| -rw-r--r-- | docs/src/drivers/pico_ppmc_es.txt | 129 | ||||
| -rw-r--r-- | docs/src/drivers/pico_ppmc_pl.txt | 111 | ||||
| -rw-r--r-- | docs/src/drivers/pluto_p.txt | 93 | ||||
| -rw-r--r-- | docs/src/drivers/pluto_p_de.txt | 93 | ||||
| -rw-r--r-- | docs/src/drivers/pluto_p_es.txt | 93 | ||||
| -rw-r--r-- | docs/src/drivers/pluto_p_pl.txt | 92 |
9 files changed, 446 insertions, 406 deletions
diff --git a/docs/src/drivers/images/pico-ppmc-math.png b/docs/src/drivers/images/pico-ppmc-math.png Binary files differnew file mode 100644 index 000000000..0877b0f74 --- /dev/null +++ b/docs/src/drivers/images/pico-ppmc-math.png diff --git a/docs/src/drivers/pico_ppmc.txt b/docs/src/drivers/pico_ppmc.txt index ed673e9fe..6e2e0e0e6 100644 --- a/docs/src/drivers/pico_ppmc.txt +++ b/docs/src/drivers/pico_ppmc.txt @@ -1,3 +1,6 @@ +:lang: en +:toc: + = Pico PPMC Pico Systems has a family of boards for doing analog servo, stepper, @@ -10,17 +13,18 @@ distinguish between boards, it simply numbers I/O channels (encoders, etc) starting from 0 on the first board. Installing: +---- +loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] +---- - loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] - -The `port_addr` parameter tells the driver what parallel port(s) to -check. By default, `<addr1>` is 0x0378, and `<addr2>` and following +The 'port_addr' parameter tells the driver what parallel port(s) to +check. By default, '<addr1>' is 0x0378, and '<addr2>' and following are not used. The driver searches the entire address -space of the enhanced parallel port(s) at `port_addr`, looking for +space of the enhanced parallel port(s) at 'port_addr', looking for any board(s) in the PPMC family. It then exports HAL pins for whatever it finds. During loading (or attempted loading) the driver prints some useful debugging messages to the kernel log, which -can be viewed with `dmesg`. +can be viewed with 'dmesg'. Up to 3 parport busses may be used, and each bus may have up to 8 devices on it. @@ -32,11 +36,11 @@ ID. According to the naming conventions the first board should always have an ID of zero. However, this driver sets the ID based on switches on the board, so it may be non-zero even if there is only one board. - - `(All s32 output) ppmc.<port>.encoder.<channel>.count` -- Encoder +* '(All s32 output) ppmc.<port>.encoder.<channel>.count' - Encoder position, in counts. - - `(All s32 output) ppmc.<port>.encoder.<channel>.delta` -- Change in +* '(All s32 output) ppmc.<port>.encoder.<channel>.delta' - Change in counts since last read, in raw encoder count units. - - (All float output) `ppmc.<port>.encoder.<channel>.velocity` -- +* '(All float output) 'ppmc.<port>.encoder.<channel>.velocity' - Velocity scaled in user units per second. On PPMC and USC this is derived from raw encoder counts per servo period, and hence is affected by encoder granularity. On UPC boards with the 8/21/09 and later @@ -45,39 +49,39 @@ on the board, so it may be non-zero even if there is only one board. to the PID HAL component to produce a more stable servo response. This function has to be enabled in the HAL command line that starts the PPMC driver, with the timestamp=0x00 option. - - `(All float output) ppmc.<port>.encoder.<channel>.position` -- +* '(All float output) ppmc.<port>.encoder.<channel>.position' - Encoder position, in user units. - - `(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable` -- +* '(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable' - Connect to axis.#.index-enable for home-to-index. This is a bidirectional HAL signal. Setting it to true causes the encoder hardware to reset the count to zero on the next encoder index pulse. The driver will detect this and set the signal back to false. - - `(PPMC float output) ppmc.<port>.DAC.<channel>.value` -- sends a +* '(PPMC float output) ppmc.<port>.DAC.<channel>.value' - sends a signed value to the 16-bit Digital to Analog Converter on the PPMC DAC16 board commanding the analog output voltage of that DAC channel. - - `(UPC bit input) ppmc.<port>.pwm.<channel>.enable` -- Enables a +* '(UPC bit input) ppmc.<port>.pwm.<channel>.enable' - Enables a PWM generator. - - `(UPC float input) ppmc.<port>.pwm.<channel>.value` -- Value +* '(UPC float input) ppmc.<port>.pwm.<channel>.value' - Value which determines the duty cycle of the PWM waveforms. The - value is divided by `pwm.<channel>.scale`, and if the result is 0.6 + value is divided by 'pwm.<channel>.scale', and if the result is 0.6 the duty cycle will be 60%, and so on. Negative values result in the duty cycle being based on the absolute value, and the direction pin is set to indicate negative. - - `(USC bit input) ppmc.<port>.stepgen.<channel>.enable` -- +* '(USC bit input) ppmc.<port>.stepgen.<channel>.enable' - Enables a step pulse generator. - - `(USC float input) ppmc.<port>.stepgen.<channel>.velocity` -- +* '(USC float input) ppmc.<port>.stepgen.<channel>.velocity' - Value which determines the step frequency. The value is multiplied - by `stepgen.<channel>.scale` , and the result is the frequency in + by 'stepgen.<channel>.scale' , and the result is the frequency in steps per second. Negative values result in the frequency being based on the absolute value, and the direction pin is set to indicate negative. - - `(All bit output) ppmc.<port>.din.<channel>.in` -- State of digital +* '(All bit output) ppmc.<port>.din.<channel>.in' - State of digital input pin, see canonical digital input. - - `(All bit output) ppmc.<port>.din.<channel>.in-not` -- Inverted +* '(All bit output) ppmc.<port>.din.<channel>.in-not' - Inverted state of digital input pin, see canonical digital input. - - `(All bit input) ppmc.<port>.dout.<channel>.out` -- Value to be +* '(All bit input) ppmc.<port>.dout.<channel>.out' - Value to be written to digital output, see canonical digital output. - - `(Option float input) ppmc.<port>.DAC8-<channel>.value` -- Value to +* '(Option float input) ppmc.<port>.DAC8-<channel>.value' - Value to be written to analog output, range from 0 to 255. This sends 8 output bits to J8, which should have a Spindle DAC board connected to it. 0 corresponds to zero Volts, 255 corresponds to 10 @@ -86,7 +90,7 @@ on the board, so it may be non-zero even if there is only one board. (minus when on). You must specify extradac = 0x00 on the HAL command line that loads the PPMC driver to enable this function on the first USC ur UPC board. - - `(Option bit input) ppmc.<port>.dout.<channel>.out` -- Value to be +* '(Option bit input) ppmc.<port>.dout.<channel>.out' - Value to be written to one of the 8 extra digital output pins on J8. You must specify extradout = 0x00 on the HAL command line that loads the ppmc driver to enable this function on the first USC or UPC @@ -96,65 +100,65 @@ on the board, so it may be non-zero even if there is only one board. == Parameters - - `(All float) ppmc.<port>.enc.<channel>.scale` -- The number of +* '(All float) ppmc.<port>.enc.<channel>.scale' - The number of counts / user unit (to convert from counts to units). - - `(UPC float) ppmc.<port>.pwm.<channel-range>.freq` -- The PWM +* '(UPC float) ppmc.<port>.pwm.<channel-range>.freq' - The PWM carrier frequency, in Hz. Applies to a group of four - consecutive PWM generators, as indicated by `<channel-range>`. Minimum + consecutive PWM generators, as indicated by '<channel-range>'. Minimum is 610Hz, maximum is 500KHz. - - `(PPMC float) ppmc.<port>.DAC.<channel>.scale` -- Sets scale +* '(PPMC float) ppmc.<port>.DAC.<channel>.scale' - Sets scale of DAC16 output channel such that an output value equal to the 1/scale - value will produce an output of + or -- value Volts. So, if the scale + value will produce an output of + or - value Volts. So, if the scale parameter is 0.1 and you send a value of 0.5, the output will be 5.0 Volts. - - `(UPC float) ppmc.<port>.pwm.<channel>.scale` -- Scaling for PWM - generator. If `scale` is X, then the duty cycle will be 100% when the - `value` pin is X (or -X). - - `(UPC float) ppmc.<port>.pwm.<channel>.max-dc` -- Maximum duty +* '(UPC float) ppmc.<port>.pwm.<channel>.scale' - Scaling for PWM + generator. If 'scale' is X, then the duty cycle will be 100% when the + 'value' pin is X (or -X). +* '(UPC float) ppmc.<port>.pwm.<channel>.max-dc' - Maximum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.min-dc` -- Minimum duty +* '(UPC float) ppmc.<port>.pwm.<channel>.min-dc' - Minimum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle` -- Actual duty +* '(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle' - Actual duty cycle (used mostly for troubleshooting.) - - `(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap` -- If true, the +* '(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap' - If true, the PWM generator will generate a short sequence of pulses of both polarities when E-stop goes false, to charge the bootstrap capacitors used on some MOSFET gate drivers. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time` -- Sets +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time' - Sets minimum time between direction change and step pulse, in units of 100ns. Applies to a group of four consecutive step generators, - as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width` -- Sets + as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width' - Sets width of step pulses, in units of 100ns. Applies to a group - of four consecutive step generators, as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min` -- Sets - minimum time between pulses, in units of 100ns. The maximum step rate is - latexmath:[$\frac{1}{ ( 100ns * ( pulse\-width + pulse\-space\-min )) }$]. - Applies to a group of four consecutive step generators, - as indicated by `<channel-range>`. - - `(USC float) ppmc.<port>.stepgen.<channel>.scale` -- Scaling for + of four consecutive step generators, as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min' - Sets + minimum time between pulses, in units of 100ns. + Applies to a group of four consecutive step generators, as indicated by + '<channel-range>'. The maximum step rate is: + image:images/pico-ppmc-math.png[] +* '(USC float) ppmc.<port>.stepgen.<channel>.scale' - Scaling for step pulse generator. The step frequency in Hz is the - absolute value of `velocity` * `scale`. - - `(USC float) ppmc.<port>.stepgen.<channel>.max-vel` -- The maximum - value for `velocity`. Commands greater than `max-vel` will be clamped. + absolute value of 'velocity' * 'scale'. +* '(USC float) ppmc.<port>.stepgen.<channel>.max-vel' - The maximum + value for 'velocity'. Commands greater than 'max-vel' will be clamped. Also applies to negative values. (The absolute value is clamped.) - - `(USC float) ppmc.<port>.stepgen.<channel>.frequency` -- Actual +* '(USC float) ppmc.<port>.stepgen.<channel>.frequency' - Actual step pulse frequency in Hz (used mostly for troubleshooting.) - - `(Option float) ppmc.<port>.DAC8.<channel>.scale` -- Sets scale +* '(Option float) ppmc.<port>.DAC8.<channel>.scale' - Sets scale of extra DAC output such that an output value equal to scale gives a magnitude of 10.0 V output. (The sign of the output is set by jumpers and/or other digital outputs.) - - `(Option bit) ppmc.<port>.dout.<channel>.invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output, see canonical digital output. - - `(Option bit) ppmc.<port>.dout.<channel>.invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output pin of J8, see canonical digital output. == Functions - - `(All funct) ppmc.<port>.read` -- Reads all inputs (digital inputs +* '(All funct) ppmc.<port>.read' - Reads all inputs (digital inputs and encoder counters) on one port. These reads are organized into blocks of contiguous registers to be read in a block to minimize CPU overhead. - - `(All funct) ppmc.<port>.write` -- Writes all outputs (digital +* '(All funct) ppmc.<port>.write' - Writes all outputs (digital outputs, stepgens, PWMs) on one port. These writes are organized into blocks of contiguous registers to be written in a block to minimize CPU overhead. diff --git a/docs/src/drivers/pico_ppmc_de.txt b/docs/src/drivers/pico_ppmc_de.txt index 07aa7405f..a43952def 100644 --- a/docs/src/drivers/pico_ppmc_de.txt +++ b/docs/src/drivers/pico_ppmc_de.txt @@ -1,3 +1,6 @@ +:lang: de +:toc: + = Pico PPMC Pico Systems has a family of boards for doing analog servo, stepper, @@ -10,17 +13,18 @@ distinguish between boards, it simply numbers I/O channels (encoders, etc) starting from 0 on the first board. Installing: +---- +loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] +---- - loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] - -The `port_addr` parameter tells the driver what parallel port(s) to -check. By default, `<addr1>` is 0x0378, and `<addr2>` and following +The 'port_addr' parameter tells the driver what parallel port(s) to +check. By default, '<addr1>' is 0x0378, and '<addr2>' and following are not used. The driver searches the entire address -space of the enhanced parallel port(s) at `port_addr`, looking for +space of the enhanced parallel port(s) at 'port_addr', looking for any board(s) in the PPMC family. It then exports HAL pins for whatever it finds. During loading (or attempted loading) the driver prints some useful debugging messages to the kernel log, which -can be viewed with `dmesg`. +can be viewed with 'dmesg'. Up to 3 parport busses may be used, and each bus may have up to 8 devices on it. @@ -32,11 +36,11 @@ ID. According to the naming conventions the first board should always have an ID of zero. However, this driver sets the ID based on switches on the board, so it may be non-zero even if there is only one board. - - `(All s32 output) ppmc.<port>.encoder.<channel>.count` -- Encoder +* '(All s32 output) ppmc.<port>.encoder.<channel>.count' - Encoder position, in counts. - - `(All s32 output) ppmc.<port>.encoder.<channel>.delta` -- Change in +* '(All s32 output) ppmc.<port>.encoder.<channel>.delta' - Change in counts since last read, in raw encoder count units. - - (All float output) `ppmc.<port>.encoder.<channel>.velocity` -- +* '(All float output) 'ppmc.<port>.encoder.<channel>.velocity' - Velocity scaled in user units per second. On PPMC and USC this is derived from raw encoder counts per servo period, and hence is affected by encoder granularity. On UPC boards with the 8/21/09 and later @@ -45,36 +49,39 @@ on the board, so it may be non-zero even if there is only one board. to the PID HAL component to produce a more stable servo response. This function has to be enabled in the HAL command line that starts the PPMC driver, with the timestamp=0x00 option. - - `(All float output) ppmc.<port>.encoder.<channel>.position` -- +* '(All float output) ppmc.<port>.encoder.<channel>.position' - Encoder position, in user units. - - `(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable` -- +* '(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable' - Connect to axis.#.index-enable for home-to-index. This is a bidirectional HAL signal. Setting it to true causes the encoder hardware to reset the count to zero on the next encoder index pulse. The driver will detect this and set the signal back to false. - - `(UPC bit input) ppmc.<port>.pwm.<channel>.enable` -- Enables a +* '(PPMC float output) ppmc.<port>.DAC.<channel>.value' - sends a + signed value to the 16-bit Digital to Analog Converter on the PPMC DAC16 + board commanding the analog output voltage of that DAC channel. +* '(UPC bit input) ppmc.<port>.pwm.<channel>.enable' - Enables a PWM generator. - - `(UPC float input) ppmc.<port>.pwm.<channel>.value` -- Value +* '(UPC float input) ppmc.<port>.pwm.<channel>.value' - Value which determines the duty cycle of the PWM waveforms. The - value is divided by `pwm.<channel>.scale`, and if the result is 0.6 + value is divided by 'pwm.<channel>.scale', and if the result is 0.6 the duty cycle will be 60%, and so on. Negative values result in the duty cycle being based on the absolute value, and the direction pin is set to indicate negative. - - `(USC bit input) ppmc.<port>.stepgen.<channel>.enable` -- +* '(USC bit input) ppmc.<port>.stepgen.<channel>.enable' - Enables a step pulse generator. - - `(USC float input) ppmc.<port>.stepgen.<channel>.velocity` -- +* '(USC float input) ppmc.<port>.stepgen.<channel>.velocity' - Value which determines the step frequency. The value is multiplied - by `stepgen.<channel>.scale` , and the result is the frequency in + by 'stepgen.<channel>.scale' , and the result is the frequency in steps per second. Negative values result in the frequency being based on the absolute value, and the direction pin is set to indicate negative. - - `(All bit output) ppmc.<port>.in-<channel>` -- State of digital +* '(All bit output) ppmc.<port>.din.<channel>.in' - State of digital input pin, see canonical digital input. - - `(All bit output) ppmc.<port>.in.<channel>-not` -- Inverted +* '(All bit output) ppmc.<port>.din.<channel>.in-not' - Inverted state of digital input pin, see canonical digital input. - - `(All bit input) ppmc.<port>.out-<channel>` -- Value to be - written to digital output, seen canonical digital output. - - `(Option float input) ppmc.<port>.DAC8-<channel>.value` -- Value to +* '(All bit input) ppmc.<port>.dout.<channel>.out' - Value to be + written to digital output, see canonical digital output. +* '(Option float input) ppmc.<port>.DAC8-<channel>.value' - Value to be written to analog output, range from 0 to 255. This sends 8 output bits to J8, which should have a Spindle DAC board connected to it. 0 corresponds to zero Volts, 255 corresponds to 10 @@ -83,73 +90,77 @@ on the board, so it may be non-zero even if there is only one board. (minus when on). You must specify extradac = 0x00 on the HAL command line that loads the PPMC driver to enable this function on the first USC ur UPC board. - - `(Option bit input) ppmc.<port>.dout-<channel>.out` -- Value to be +* '(Option bit input) ppmc.<port>.dout.<channel>.out' - Value to be written to one of the 8 extra digital output pins on J8. You must specify extradout = 0x00 on the HAL command line that loads the ppmc driver to enable this function on the first USC or UPC board. extradac and extradout are mutually exclusive features as they - use the same signal lines for different purposes. + use the same signal lines for different purposes. These output pins + will be enumerated after the standard digital outputs of the board. == Parameters - - `(All float) ppmc.<port>.enc.<channel>.scale` -- The number of +* '(All float) ppmc.<port>.enc.<channel>.scale' - The number of counts / user unit (to convert from counts to units). - - `(UPC float) ppmc.<port>.pwm.<channel-range>.freq` -- The PWM +* '(UPC float) ppmc.<port>.pwm.<channel-range>.freq' - The PWM carrier frequency, in Hz. Applies to a group of four - consecutive PWM generators, as indicated by `<channel-range>`. Minimum + consecutive PWM generators, as indicated by '<channel-range>'. Minimum is 610Hz, maximum is 500KHz. - - `(UPC float) ppmc.<port>.pwm.<channel>.scale` -- Scaling for PWM - generator. If `scale` is X, then the duty cycle will be 100% when the - `value` pin is X (or -X). - - `(UPC float) ppmc.<port>.pwm.<channel>.max-dc` -- Maximum duty +* '(PPMC float) ppmc.<port>.DAC.<channel>.scale' - Sets scale + of DAC16 output channel such that an output value equal to the 1/scale + value will produce an output of + or - value Volts. So, if the scale + parameter is 0.1 and you send a value of 0.5, the output will be 5.0 Volts. +* '(UPC float) ppmc.<port>.pwm.<channel>.scale' - Scaling for PWM + generator. If 'scale' is X, then the duty cycle will be 100% when the + 'value' pin is X (or -X). +* '(UPC float) ppmc.<port>.pwm.<channel>.max-dc' - Maximum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.min-dc` -- Minimum duty +* '(UPC float) ppmc.<port>.pwm.<channel>.min-dc' - Minimum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle` -- Actual duty +* '(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle' - Actual duty cycle (used mostly for troubleshooting.) - - `(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap` -- If true, the +* '(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap' - If true, the PWM generator will generate a short sequence of pulses of both polarities when E-stop goes false, to charge the bootstrap capacitors used on some MOSFET gate drivers. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time` -- - Sets minimum time between direction change and step pulse, in - units of 100ns. Applies to a group of four consecutive PWM generators, - as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width` -- - Sets width of step pulses, in units of 100ns. Applies to a group - of four consecutive PWM generators, as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min` - -- Sets minimum time between pulses, in units of 100ns. - The maximum step rate is - latexmath:[$ \frac{1}{ ( 100ns * ( `pulse-width` + `pulse-space-min` )) } $]. - Applies to a group of four consecutive PWM generators, - as indicated by `<channel-range>`. - - `(USC float) ppmc.<port>.stepgen.<channel>.scale` -- Scaling for +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time' - Sets + minimum time between direction change and step pulse, in + units of 100ns. Applies to a group of four consecutive step generators, + as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width' - Sets + width of step pulses, in units of 100ns. Applies to a group + of four consecutive step generators, as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min' - Sets + minimum time between pulses, in units of 100ns. + Applies to a group of four consecutive step generators, as indicated by + '<channel-range>'. The maximum step rate is: + image:images/pico-ppmc-math.png[] +* '(USC float) ppmc.<port>.stepgen.<channel>.scale' - Scaling for step pulse generator. The step frequency in Hz is the - absolute value of `velocity` * `scale`. - - `(USC float) ppmc.<port>.stepgen.<channel>.max-vel` -- The maximum - value for `velocity`. Commands greater than `max-vel` will be clamped. + absolute value of 'velocity' * 'scale'. +* '(USC float) ppmc.<port>.stepgen.<channel>.max-vel' - The maximum + value for 'velocity'. Commands greater than 'max-vel' will be clamped. Also applies to negative values. (The absolute value is clamped.) - - `(USC float) ppmc.<port>.stepgen.<channel>.frequency` -- Actual +* '(USC float) ppmc.<port>.stepgen.<channel>.frequency' - Actual step pulse frequency in Hz (used mostly for troubleshooting.) - - `(Option float) ppmc.<port>.DAC8.<channel>.scale` -- Sets scale +* '(Option float) ppmc.<port>.DAC8.<channel>.scale' - Sets scale of extra DAC output such that an output value equal to scale gives a magnitude of 10.0 V output. (The sign of the output is set by jumpers and/or other digital outputs.) - - `(Option bit) ppmc.<port>.out.<channel>-invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output, see canonical digital output. - - `(Option bit) ppmc.<port>.dout.<channel>-invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output pin of J8, see canonical digital output. == Functions - - `(All funct) ppmc.<port>.read` -- Reads all inputs (digital inputs +* '(All funct) ppmc.<port>.read' - Reads all inputs (digital inputs and encoder counters) on one port. These reads are organized into blocks of contiguous registers to be read in a block to minimize CPU overhead. - - `(All funct) ppmc.<port>.write` -- Writes all outputs (digital +* '(All funct) ppmc.<port>.write' - Writes all outputs (digital outputs, stepgens, PWMs) on one port. - These reads are organized into blocks of contiguous registers to be - read in a block to minimize CPU overhead. + These writes are organized into blocks of contiguous registers to be + written in a block to minimize CPU overhead. diff --git a/docs/src/drivers/pico_ppmc_es.txt b/docs/src/drivers/pico_ppmc_es.txt index 07aa7405f..c4a3645af 100644 --- a/docs/src/drivers/pico_ppmc_es.txt +++ b/docs/src/drivers/pico_ppmc_es.txt @@ -1,3 +1,6 @@ +:lang: es +:toc: + = Pico PPMC Pico Systems has a family of boards for doing analog servo, stepper, @@ -10,17 +13,18 @@ distinguish between boards, it simply numbers I/O channels (encoders, etc) starting from 0 on the first board. Installing: +---- +loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] +---- - loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] - -The `port_addr` parameter tells the driver what parallel port(s) to -check. By default, `<addr1>` is 0x0378, and `<addr2>` and following +The 'port_addr' parameter tells the driver what parallel port(s) to +check. By default, '<addr1>' is 0x0378, and '<addr2>' and following are not used. The driver searches the entire address -space of the enhanced parallel port(s) at `port_addr`, looking for +space of the enhanced parallel port(s) at 'port_addr', looking for any board(s) in the PPMC family. It then exports HAL pins for whatever it finds. During loading (or attempted loading) the driver prints some useful debugging messages to the kernel log, which -can be viewed with `dmesg`. +can be viewed with 'dmesg'. Up to 3 parport busses may be used, and each bus may have up to 8 devices on it. @@ -32,11 +36,11 @@ ID. According to the naming conventions the first board should always have an ID of zero. However, this driver sets the ID based on switches on the board, so it may be non-zero even if there is only one board. - - `(All s32 output) ppmc.<port>.encoder.<channel>.count` -- Encoder +* '(All s32 output) ppmc.<port>.encoder.<channel>.count' - Encoder position, in counts. - - `(All s32 output) ppmc.<port>.encoder.<channel>.delta` -- Change in +* '(All s32 output) ppmc.<port>.encoder.<channel>.delta' - Change in counts since last read, in raw encoder count units. - - (All float output) `ppmc.<port>.encoder.<channel>.velocity` -- +* '(All float output) 'ppmc.<port>.encoder.<channel>.velocity' - Velocity scaled in user units per second. On PPMC and USC this is derived from raw encoder counts per servo period, and hence is affected by encoder granularity. On UPC boards with the 8/21/09 and later @@ -45,36 +49,39 @@ on the board, so it may be non-zero even if there is only one board. to the PID HAL component to produce a more stable servo response. This function has to be enabled in the HAL command line that starts the PPMC driver, with the timestamp=0x00 option. - - `(All float output) ppmc.<port>.encoder.<channel>.position` -- +* '(All float output) ppmc.<port>.encoder.<channel>.position' - Encoder position, in user units. - - `(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable` -- +* '(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable' - Connect to axis.#.index-enable for home-to-index. This is a bidirectional HAL signal. Setting it to true causes the encoder hardware to reset the count to zero on the next encoder index pulse. The driver will detect this and set the signal back to false. - - `(UPC bit input) ppmc.<port>.pwm.<channel>.enable` -- Enables a +* '(PPMC float output) ppmc.<port>.DAC.<channel>.value' - sends a + signed value to the 16-bit Digital to Analog Converter on the PPMC DAC16 + board commanding the analog output voltage of that DAC channel. +* '(UPC bit input) ppmc.<port>.pwm.<channel>.enable' - Enables a PWM generator. - - `(UPC float input) ppmc.<port>.pwm.<channel>.value` -- Value +* '(UPC float input) ppmc.<port>.pwm.<channel>.value' - Value which determines the duty cycle of the PWM waveforms. The - value is divided by `pwm.<channel>.scale`, and if the result is 0.6 + value is divided by 'pwm.<channel>.scale', and if the result is 0.6 the duty cycle will be 60%, and so on. Negative values result in the duty cycle being based on the absolute value, and the direction pin is set to indicate negative. - - `(USC bit input) ppmc.<port>.stepgen.<channel>.enable` -- +* '(USC bit input) ppmc.<port>.stepgen.<channel>.enable' - Enables a step pulse generator. - - `(USC float input) ppmc.<port>.stepgen.<channel>.velocity` -- +* '(USC float input) ppmc.<port>.stepgen.<channel>.velocity' - Value which determines the step frequency. The value is multiplied - by `stepgen.<channel>.scale` , and the result is the frequency in + by 'stepgen.<channel>.scale' , and the result is the frequency in steps per second. Negative values result in the frequency being based on the absolute value, and the direction pin is set to indicate negative. - - `(All bit output) ppmc.<port>.in-<channel>` -- State of digital +* '(All bit output) ppmc.<port>.din.<channel>.in' - State of digital input pin, see canonical digital input. - - `(All bit output) ppmc.<port>.in.<channel>-not` -- Inverted +* '(All bit output) ppmc.<port>.din.<channel>.in-not' - Inverted state of digital input pin, see canonical digital input. - - `(All bit input) ppmc.<port>.out-<channel>` -- Value to be - written to digital output, seen canonical digital output. - - `(Option float input) ppmc.<port>.DAC8-<channel>.value` -- Value to +* '(All bit input) ppmc.<port>.dout.<channel>.out' - Value to be + written to digital output, see canonical digital output. +* '(Option float input) ppmc.<port>.DAC8-<channel>.value' - Value to be written to analog output, range from 0 to 255. This sends 8 output bits to J8, which should have a Spindle DAC board connected to it. 0 corresponds to zero Volts, 255 corresponds to 10 @@ -83,73 +90,77 @@ on the board, so it may be non-zero even if there is only one board. (minus when on). You must specify extradac = 0x00 on the HAL command line that loads the PPMC driver to enable this function on the first USC ur UPC board. - - `(Option bit input) ppmc.<port>.dout-<channel>.out` -- Value to be +* '(Option bit input) ppmc.<port>.dout.<channel>.out' - Value to be written to one of the 8 extra digital output pins on J8. You must specify extradout = 0x00 on the HAL command line that loads the ppmc driver to enable this function on the first USC or UPC board. extradac and extradout are mutually exclusive features as they - use the same signal lines for different purposes. + use the same signal lines for different purposes. These output pins + will be enumerated after the standard digital outputs of the board. == Parameters - - `(All float) ppmc.<port>.enc.<channel>.scale` -- The number of +* '(All float) ppmc.<port>.enc.<channel>.scale' - The number of counts / user unit (to convert from counts to units). - - `(UPC float) ppmc.<port>.pwm.<channel-range>.freq` -- The PWM +* '(UPC float) ppmc.<port>.pwm.<channel-range>.freq' - The PWM carrier frequency, in Hz. Applies to a group of four - consecutive PWM generators, as indicated by `<channel-range>`. Minimum + consecutive PWM generators, as indicated by '<channel-range>'. Minimum is 610Hz, maximum is 500KHz. - - `(UPC float) ppmc.<port>.pwm.<channel>.scale` -- Scaling for PWM - generator. If `scale` is X, then the duty cycle will be 100% when the - `value` pin is X (or -X). - - `(UPC float) ppmc.<port>.pwm.<channel>.max-dc` -- Maximum duty +* '(PPMC float) ppmc.<port>.DAC.<channel>.scale' - Sets scale + of DAC16 output channel such that an output value equal to the 1/scale + value will produce an output of + or - value Volts. So, if the scale + parameter is 0.1 and you send a value of 0.5, the output will be 5.0 Volts. +* '(UPC float) ppmc.<port>.pwm.<channel>.scale' - Scaling for PWM + generator. If 'scale' is X, then the duty cycle will be 100% when the + 'value' pin is X (or -X). +* '(UPC float) ppmc.<port>.pwm.<channel>.max-dc' - Maximum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.min-dc` -- Minimum duty +* '(UPC float) ppmc.<port>.pwm.<channel>.min-dc' - Minimum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle` -- Actual duty +* '(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle' - Actual duty cycle (used mostly for troubleshooting.) - - `(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap` -- If true, the +* '(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap' - If true, the PWM generator will generate a short sequence of pulses of both polarities when E-stop goes false, to charge the bootstrap capacitors used on some MOSFET gate drivers. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time` -- - Sets minimum time between direction change and step pulse, in - units of 100ns. Applies to a group of four consecutive PWM generators, - as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width` -- - Sets width of step pulses, in units of 100ns. Applies to a group - of four consecutive PWM generators, as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min` - -- Sets minimum time between pulses, in units of 100ns. - The maximum step rate is - latexmath:[$ \frac{1}{ ( 100ns * ( `pulse-width` + `pulse-space-min` )) } $]. - Applies to a group of four consecutive PWM generators, - as indicated by `<channel-range>`. - - `(USC float) ppmc.<port>.stepgen.<channel>.scale` -- Scaling for +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time' - Sets + minimum time between direction change and step pulse, in + units of 100ns. Applies to a group of four consecutive step generators, + as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width' - Sets + width of step pulses, in units of 100ns. Applies to a group + of four consecutive step generators, as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min' - Sets + minimum time between pulses, in units of 100ns. + Applies to a group of four consecutive step generators, as indicated by + '<channel-range>'. The maximum step rate is: + image:images/pico-ppmc-math.png[] +* '(USC float) ppmc.<port>.stepgen.<channel>.scale' - Scaling for step pulse generator. The step frequency in Hz is the - absolute value of `velocity` * `scale`. - - `(USC float) ppmc.<port>.stepgen.<channel>.max-vel` -- The maximum - value for `velocity`. Commands greater than `max-vel` will be clamped. + absolute value of 'velocity' * 'scale'. +* '(USC float) ppmc.<port>.stepgen.<channel>.max-vel' - The maximum + value for 'velocity'. Commands greater than 'max-vel' will be clamped. Also applies to negative values. (The absolute value is clamped.) - - `(USC float) ppmc.<port>.stepgen.<channel>.frequency` -- Actual +* '(USC float) ppmc.<port>.stepgen.<channel>.frequency' - Actual step pulse frequency in Hz (used mostly for troubleshooting.) - - `(Option float) ppmc.<port>.DAC8.<channel>.scale` -- Sets scale +* '(Option float) ppmc.<port>.DAC8.<channel>.scale' - Sets scale of extra DAC output such that an output value equal to scale gives a magnitude of 10.0 V output. (The sign of the output is set by jumpers and/or other digital outputs.) - - `(Option bit) ppmc.<port>.out.<channel>-invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output, see canonical digital output. - - `(Option bit) ppmc.<port>.dout.<channel>-invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output pin of J8, see canonical digital output. == Functions - - `(All funct) ppmc.<port>.read` -- Reads all inputs (digital inputs +* '(All funct) ppmc.<port>.read' - Reads all inputs (digital inputs and encoder counters) on one port. These reads are organized into blocks of contiguous registers to be read in a block to minimize CPU overhead. - - `(All funct) ppmc.<port>.write` -- Writes all outputs (digital +* '(All funct) ppmc.<port>.write' - Writes all outputs (digital outputs, stepgens, PWMs) on one port. - These reads are organized into blocks of contiguous registers to be - read in a block to minimize CPU overhead. + These writes are organized into blocks of contiguous registers to be + written in a block to minimize CPU overhead. diff --git a/docs/src/drivers/pico_ppmc_pl.txt b/docs/src/drivers/pico_ppmc_pl.txt index a73f1ea79..dab2df424 100644 --- a/docs/src/drivers/pico_ppmc_pl.txt +++ b/docs/src/drivers/pico_ppmc_pl.txt @@ -1,3 +1,5 @@ +:toc: + = Pico PPMC Pico Systems has a family of boards for doing analog servo, stepper, @@ -10,17 +12,18 @@ distinguish between boards, it simply numbers I/O channels (encoders, etc) starting from 0 on the first board. Installing: +---- +loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] +---- - loadrt hal_ppmc port_addr=<addr1>[,<addr2>[,<addr3>...]] - -The `port_addr` parameter tells the driver what parallel port(s) to -check. By default, `<addr1>` is 0x0378, and `<addr2>` and following +The 'port_addr' parameter tells the driver what parallel port(s) to +check. By default, '<addr1>' is 0x0378, and '<addr2>' and following are not used. The driver searches the entire address -space of the enhanced parallel port(s) at `port_addr`, looking for +space of the enhanced parallel port(s) at 'port_addr', looking for any board(s) in the PPMC family. It then exports HAL pins for whatever it finds. During loading (or attempted loading) the driver prints some useful debugging messages to the kernel log, which -can be viewed with `dmesg`. +can be viewed with 'dmesg'. Up to 3 parport busses may be used, and each bus may have up to 8 devices on it. @@ -32,11 +35,11 @@ ID. According to the naming conventions the first board should always have an ID of zero. However, this driver sets the ID based on switches on the board, so it may be non-zero even if there is only one board. - - `(All s32 output) ppmc.<port>.encoder.<channel>.count` -- Encoder +* '(All s32 output) ppmc.<port>.encoder.<channel>.count' - Encoder position, in counts. - - `(All s32 output) ppmc.<port>.encoder.<channel>.delta` -- Change in +* '(All s32 output) ppmc.<port>.encoder.<channel>.delta' - Change in counts since last read, in raw encoder count units. - - (All float output) `ppmc.<port>.encoder.<channel>.velocity` -- +* '(All float output) 'ppmc.<port>.encoder.<channel>.velocity' - Velocity scaled in user units per second. On PPMC and USC this is derived from raw encoder counts per servo period, and hence is affected by encoder granularity. On UPC boards with the 8/21/09 and later @@ -45,39 +48,39 @@ on the board, so it may be non-zero even if there is only one board. to the PID HAL component to produce a more stable servo response. This function has to be enabled in the HAL command line that starts the PPMC driver, with the timestamp=0x00 option. - - `(All float output) ppmc.<port>.encoder.<channel>.position` -- +* '(All float output) ppmc.<port>.encoder.<channel>.position' - Encoder position, in user units. - - `(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable` -- +* '(All bit bidir) ppmc.<port>.encoder.<channel>.index-enable' - Connect to axis.#.index-enable for home-to-index. This is a bidirectional HAL signal. Setting it to true causes the encoder hardware to reset the count to zero on the next encoder index pulse. The driver will detect this and set the signal back to false. - - `(PPMC float output) ppmc.<port>.DAC.<channel>.value` -- sends a +* '(PPMC float output) ppmc.<port>.DAC.<channel>.value' - sends a signed value to the 16-bit Digital to Analog Converter on the PPMC DAC16 board commanding the analog output voltage of that DAC channel. - - `(UPC bit input) ppmc.<port>.pwm.<channel>.enable` -- Enables a +* '(UPC bit input) ppmc.<port>.pwm.<channel>.enable' - Enables a PWM generator. - - `(UPC float input) ppmc.<port>.pwm.<channel>.value` -- Value +* '(UPC float input) ppmc.<port>.pwm.<channel>.value' - Value which determines the duty cycle of the PWM waveforms. The - value is divided by `pwm.<channel>.scale`, and if the result is 0.6 + value is divided by 'pwm.<channel>.scale', and if the result is 0.6 the duty cycle will be 60%, and so on. Negative values result in the duty cycle being based on the absolute value, and the direction pin is set to indicate negative. - - `(USC bit input) ppmc.<port>.stepgen.<channel>.enable` -- +* '(USC bit input) ppmc.<port>.stepgen.<channel>.enable' - Enables a step pulse generator. - - `(USC float input) ppmc.<port>.stepgen.<channel>.velocity` -- +* '(USC float input) ppmc.<port>.stepgen.<channel>.velocity' - Value which determines the step frequency. The value is multiplied - by `stepgen.<channel>.scale` , and the result is the frequency in + by 'stepgen.<channel>.scale' , and the result is the frequency in steps per second. Negative values result in the frequency being based on the absolute value, and the direction pin is set to indicate negative. - - `(All bit output) ppmc.<port>.din.<channel>.in` -- State of digital +* '(All bit output) ppmc.<port>.din.<channel>.in' - State of digital input pin, see canonical digital input. - - `(All bit output) ppmc.<port>.din.<channel>.in-not` -- Inverted +* '(All bit output) ppmc.<port>.din.<channel>.in-not' - Inverted state of digital input pin, see canonical digital input. - - `(All bit input) ppmc.<port>.dout.<channel>.out` -- Value to be +* '(All bit input) ppmc.<port>.dout.<channel>.out' - Value to be written to digital output, see canonical digital output. - - `(Option float input) ppmc.<port>.DAC8-<channel>.value` -- Value to +* '(Option float input) ppmc.<port>.DAC8-<channel>.value' - Value to be written to analog output, range from 0 to 255. This sends 8 output bits to J8, which should have a Spindle DAC board connected to it. 0 corresponds to zero Volts, 255 corresponds to 10 @@ -86,7 +89,7 @@ on the board, so it may be non-zero even if there is only one board. (minus when on). You must specify extradac = 0x00 on the HAL command line that loads the PPMC driver to enable this function on the first USC ur UPC board. - - `(Option bit input) ppmc.<port>.dout.<channel>.out` -- Value to be +* '(Option bit input) ppmc.<port>.dout.<channel>.out' - Value to be written to one of the 8 extra digital output pins on J8. You must specify extradout = 0x00 on the HAL command line that loads the ppmc driver to enable this function on the first USC or UPC @@ -96,65 +99,65 @@ on the board, so it may be non-zero even if there is only one board. == Parameters - - `(All float) ppmc.<port>.enc.<channel>.scale` -- The number of +* '(All float) ppmc.<port>.enc.<channel>.scale' - The number of counts / user unit (to convert from counts to units). - - `(UPC float) ppmc.<port>.pwm.<channel-range>.freq` -- The PWM +* '(UPC float) ppmc.<port>.pwm.<channel-range>.freq' - The PWM carrier frequency, in Hz. Applies to a group of four - consecutive PWM generators, as indicated by `<channel-range>`. Minimum + consecutive PWM generators, as indicated by '<channel-range>'. Minimum is 610Hz, maximum is 500KHz. - - `(PPMC float) ppmc.<port>.DAC.<channel>.scale` -- Sets scale +* '(PPMC float) ppmc.<port>.DAC.<channel>.scale' - Sets scale of DAC16 output channel such that an output value equal to the 1/scale - value will produce an output of + or -- value Volts. So, if the scale + value will produce an output of + or - value Volts. So, if the scale parameter is 0.1 and you send a value of 0.5, the output will be 5.0 Volts. - - `(UPC float) ppmc.<port>.pwm.<channel>.scale` -- Scaling for PWM - generator. If `scale` is X, then the duty cycle will be 100% when the - `value` pin is X (or -X). - - `(UPC float) ppmc.<port>.pwm.<channel>.max-dc` -- Maximum duty +* '(UPC float) ppmc.<port>.pwm.<channel>.scale' - Scaling for PWM + generator. If 'scale' is X, then the duty cycle will be 100% when the + 'value' pin is X (or -X). +* '(UPC float) ppmc.<port>.pwm.<channel>.max-dc' - Maximum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.min-dc` -- Minimum duty +* '(UPC float) ppmc.<port>.pwm.<channel>.min-dc' - Minimum duty cycle, from 0.0 to 1.0. - - `(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle` -- Actual duty +* '(UPC float) ppmc.<port>.pwm.<channel>.duty-cycle' - Actual duty cycle (used mostly for troubleshooting.) - - `(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap` -- If true, the +* '(UPC bit) ppmc.<port>.pwm.<channel>.bootstrap' - If true, the PWM generator will generate a short sequence of pulses of both polarities when E-stop goes false, to charge the bootstrap capacitors used on some MOSFET gate drivers. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time` -- Sets +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.setup-time' - Sets minimum time between direction change and step pulse, in units of 100ns. Applies to a group of four consecutive step generators, - as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width` -- Sets + as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-width' - Sets width of step pulses, in units of 100ns. Applies to a group - of four consecutive step generators, as indicated by `<channel-range>`. - - `(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min` -- Sets - minimum time between pulses, in units of 100ns. The maximum step rate is - latexmath:[[\frac{1}{ ( 100ns * ( `pulse-width` + `pulse-space-min` )) } \]]. - Applies to a group of four consecutive step generators, - as indicated by `<channel-range>`. - - `(USC float) ppmc.<port>.stepgen.<channel>.scale` -- Scaling for + of four consecutive step generators, as indicated by '<channel-range>'. +* '(USC u32) ppmc.<port>.stepgen.<channel-range>.pulse-space-min' - Sets + minimum time between pulses, in units of 100ns. + Applies to a group of four consecutive step generators, as indicated by + '<channel-range>'. The maximum step rate is: + image:images/pico-ppmc-math.png[] +* '(USC float) ppmc.<port>.stepgen.<channel>.scale' - Scaling for step pulse generator. The step frequency in Hz is the - absolute value of `velocity` * `scale`. - - `(USC float) ppmc.<port>.stepgen.<channel>.max-vel` -- The maximum - value for `velocity`. Commands greater than `max-vel` will be clamped. + absolute value of 'velocity' * 'scale'. +* '(USC float) ppmc.<port>.stepgen.<channel>.max-vel' - The maximum + value for 'velocity'. Commands greater than 'max-vel' will be clamped. Also applies to negative values. (The absolute value is clamped.) - - `(USC float) ppmc.<port>.stepgen.<channel>.frequency` -- Actual +* '(USC float) ppmc.<port>.stepgen.<channel>.frequency' - Actual step pulse frequency in Hz (used mostly for troubleshooting.) - - `(Option float) ppmc.<port>.DAC8.<channel>.scale` -- Sets scale +* '(Option float) ppmc.<port>.DAC8.<channel>.scale' - Sets scale of extra DAC output such that an output value equal to scale gives a magnitude of 10.0 V output. (The sign of the output is set by jumpers and/or other digital outputs.) - - `(Option bit) ppmc.<port>.dout.<channel>.invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output, see canonical digital output. - - `(Option bit) ppmc.<port>.dout.<channel>.invert` -- Inverts a +* '(Option bit) ppmc.<port>.dout.<channel>.invert' - Inverts a digital output pin of J8, see canonical digital output. == Functions - - `(All funct) ppmc.<port>.read` -- Reads all inputs (digital inputs +* '(All funct) ppmc.<port>.read' - Reads all inputs (digital inputs and encoder counters) on one port. These reads are organized into blocks of contiguous registers to be read in a block to minimize CPU overhead. - - `(All funct) ppmc.<port>.write` -- Writes all outputs (digital +* '(All funct) ppmc.<port>.write' - Writes all outputs (digital outputs, stepgens, PWMs) on one port. These writes are organized into blocks of contiguous registers to be written in a block to minimize CPU overhead. diff --git a/docs/src/drivers/pluto_p.txt b/docs/src/drivers/pluto_p.txt index 2d1bcf21a..af0924b54 100644 --- a/docs/src/drivers/pluto_p.txt +++ b/docs/src/drivers/pluto_p.txt @@ -1,3 +1,6 @@ +:lang: en +:toc: + = Pluto-P == General Info @@ -7,44 +10,44 @@ ACEX1K(((ACEX1K))) chip from Altera. === Requirements - . A Pluto-P board - . An EPP-compatible parallel port, configured for EPP mode in the system BIOS +. A Pluto-P board +. An EPP-compatible parallel port, configured for EPP mode in the system BIOS === Connectors - - The Pluto-P board is shipped with the left connector presoldered, with +* The Pluto-P board is shipped with the left connector presoldered, with the key in the indicated position. The other connectors are unpopulated. There does not seem to be a standard 12-pin IDC connector, but some of the pins of a 16P connector can hang off the board next to QA3/QZ3. - - The bottom and right connectors are on the same .1" grid, but the left +* The bottom and right connectors are on the same .1" grid, but the left connector is not. If OUT2…OUT9 are not required, a single IDC connector can span the bottom connector and the bottom two rows of the right connector. === Physical Pins - - Read the ACEX1K datasheet for information about input and output - voltage thresholds. The pins are all configured in "LVTTL/LVCMOS" mode +* Read the ACEX1K datasheet for information about input and output + voltage thresholds. The pins are all configured in 'LVTTL/LVCMOS' mode and are generally compatible with 5V TTL logic. - - Before configuration and after properly exiting EMC2, all Pluto-P pins +* Before configuration and after properly exiting EMC2, all Pluto-P pins are tristated with weak pull-ups (20k-ohms min, 50k-ohms max). If the watchdog timer is enabled (the default), these pins are also tristated after an interruption of communication between EMC2 and the board. The watchdog timer takes approximately 6.5ms to activate. However, software bugs in the pluto_servo firmware or EMC2 can leave the Pluto-P pins in an undefined state. - - In pwm+dir mode, by default dir is HIGH for negative values and LOW +* In pwm+dir mode, by default dir is HIGH for negative values and LOW for positive values. To select HIGH for positive values and LOW for negative values, set the corresponding dout-NN-invert parameter TRUE to invert the signal. - - The index input is triggered on the rising edge. Initial testing has +* The index input is triggered on the rising edge. Initial testing has shown that the QZx inputs are particularly noise sensitive, due to being polled every 25ns. Digital filtering has been added to filter pulses shorter than 175ns (seven polling times). Additional external filtering on all input pins, such as a Schmitt buffer or inverter, RC filter, or differential receiver (if applicable) is recommended. - - The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA +* The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA pins. No other pins have any sort of protection for out-of-spec voltages or currents. It is up to the integrator to add appropriate isolation and protection. Traditional parallel port optoisolator boards @@ -53,33 +56,33 @@ ACEX1K(((ACEX1K))) chip from Altera. === LED - - When the device is unprogrammed, the LED glows faintly. When the +* When the device is unprogrammed, the LED glows faintly. When the device is programmed, the LED glows according to the duty cycle of PWM0 - (*LED* = *UP0* 'xor' *DOWN0*) or STEPGEN0 (*LED* = *STEP0* 'xor' - *DIR0*). + ('LED' = 'UP0' 'xor' 'DOWN0') or STEPGEN0 ('LED' = 'STEP0' 'xor' + 'DIR0'). === Power - - A small amount of current may be drawn from VCC. The available current +* A small amount of current may be drawn from VCC. The available current depends on the unregulated DC input to the board. Alternately, regulated +3.3VDC may be supplied to the FPGA through these VCC pins. The required current is not yet known, but is probably around 50mA plus I/O current. - - The regulator on the Pluto-P board is a low-dropout type. Supplying 5V +* The regulator on the Pluto-P board is a low-dropout type. Supplying 5V at the power jack will allow the regulator to work properly. === PC interface - - Only a single pluto_servo or pluto_step board is supported. +* Only a single pluto_servo or pluto_step board is supported. === Rebuilding the FPGA firmware -The `src/hal/drivers/pluto_servo_firmware/` and -`src/hal/drivers/pluto_step_firmware/` subdirectories contain the +The 'src/hal/drivers/pluto_servo_firmware/' and +'src/hal/drivers/pluto_step_firmware/' subdirectories contain the Verilog source code plus additional files used by Quartus for the FPGA firmwares. Altera's Quartus II software is required to rebuild the FPGA firmware. To rebuild the firmware from the - .hdl and other source files, open the `.qpf` file and press CTRL-L. + .hdl and other source files, open the '.qpf' file and press CTRL-L. Then, recompile EMC2. Like the HAL hardware driver, the FPGA firmware is licensed under the @@ -103,33 +106,33 @@ limit switches. This driver features: - - 4 quadrature channels with 40MHz sample rate. The counters operate in - "4x" mode. The maximum useful quadrature rate is 8191 counts per EMC2 +* 4 quadrature channels with 40MHz sample rate. The counters operate in + '4x' mode. The maximum useful quadrature rate is 8191 counts per EMC2 servo cycle, or about 8MHz for EMC2's default 1ms servo rate. - - 4 PWM channels, "up/down" or "pwm+dir" style. 4095 duty cycles from +* 4 PWM channels, 'up/down' or 'pwm+dir' style. 4095 duty cycles from -100% to +100%, including 0%. The PWM period is approximately 19.5kHz (40MHz / 2047). A PDM-like mode is also available. - - 18 digital outputs: 10 dedicated, 8 shared with PWM functions. +* 18 digital outputs: 10 dedicated, 8 shared with PWM functions. (Example: A lathe with unidirectional PWM spindle control may use 13 total digital outputs) - - 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. +* 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. (Example: A lathe with index pulse only on the spindle may use 13 total digital inputs) - - EPP communication with the PC. The EPP communication typically takes +* EPP communication with the PC. The EPP communication typically takes around 100 us on machines tested so far, enabling servo rates above 1kHz. === Pinout UPx:: - The "up" (up/down mode) or “pwm” (pwm+direction mode) signal from PWM + The 'up' (up/down mode) or 'pwm' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is always negative. The corresponding digital output invert may be set to TRUE to make UPx active low rather than active high. DNx:: - The "down" (up/down mode) or “direction” (pwm+direction mode) signal + The 'down' (up/down mode) or 'direction' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is never negative. The corresponding digital ouput invert may be set to @@ -197,12 +200,12 @@ image::images/pluto-pinout.eps[] === Input latching and output updating - - PWM duty cycles for each channel are updated at different times. - - Digital outputs OUT0 through OUT9 are all updated at the same time. +* PWM duty cycles for each channel are updated at different times. +* Digital outputs OUT0 through OUT9 are all updated at the same time. Digital outputs OUT10 through OUT17 are updated at the same time as the pwm function they are shared with. - - Digital inputs IN0 through IN19 are all latched at the same time. - - Quadrature positions for each channel are latched at different times. +* Digital inputs IN0 through IN19 are all latched at the same time. +* Quadrature positions for each channel are latched at different times. === HAL Functions, Pins and Parameters @@ -231,19 +234,19 @@ limit switches. The board features: - - 4 “step+direction” channels with 312.5kHz maximum step rate, +* 4 'step+direction' channels with 312.5kHz maximum step rate, programmable step length, space, and direction change times - - 14 dedicated digital outputs - - 16 dedicated digital inputs - - EPP communication with the PC +* 14 dedicated digital outputs +* 16 dedicated digital inputs +* EPP communication with the PC === Pinout STEPx:: - The “step” (clock) output of stepgen channel *x* + The 'step' (clock) output of stepgen channel 'x' DIRx:: - The “direction” output of stepgen channel *x* + The 'direction' output of stepgen channel 'x' INx:: Dedicated digital input #x @@ -257,7 +260,7 @@ GND:: VCC:: +3.3V regulated DC -While the “extended main connector” has a superset of signals usually +While the 'extended main connector' has a superset of signals usually found on a Step & Direction DB25 connector--4 step generators, 9 inputs, and 6 general-purpose outputs--the layout on this header is different than the layout of a standard 26-pin ribbon cable to DB25 @@ -269,19 +272,19 @@ image::images/pluto-step-pinout.eps[] === Input latching and output updating - - Step frequencies for each channel are updated at different times. - - Digital outputs are all updated at the same time. - - Digital inputs are all latched at the same time. - - Feedback positions for each channel are latched at different times. +* Step frequencies for each channel are updated at different times. +* Digital outputs are all updated at the same time. +* Digital inputs are all latched at the same time. +* Feedback positions for each channel are latched at different times. === Step Waveform Timings The firmware and driver enforce step length, space, and direction change times. Timings are rounded up to the next multiple of -latexmath:[1.6μs], with a maximum of latexmath:[49.6μs]. The timings +1.6μs, with a maximum of 49.6μs. The timings are the same as for the software stepgen component, except that -“dirhold” and “dirsetup” have been merged into a single parameter -“dirtime” which should be the maximum of the two, and that the same +'dirhold' and 'dirsetup' have been merged into a single parameter +'dirtime' which should be the maximum of the two, and that the same step timings are always applied to all channels. .Pluto-Step Timings[[fig:Pluto-Step-Timings]](((pluto-step timings))) diff --git a/docs/src/drivers/pluto_p_de.txt b/docs/src/drivers/pluto_p_de.txt index 2d1bcf21a..7f2c1e1bd 100644 --- a/docs/src/drivers/pluto_p_de.txt +++ b/docs/src/drivers/pluto_p_de.txt @@ -1,3 +1,6 @@ +:lang: de +:toc: + = Pluto-P == General Info @@ -7,44 +10,44 @@ ACEX1K(((ACEX1K))) chip from Altera. === Requirements - . A Pluto-P board - . An EPP-compatible parallel port, configured for EPP mode in the system BIOS +. A Pluto-P board +. An EPP-compatible parallel port, configured for EPP mode in the system BIOS === Connectors - - The Pluto-P board is shipped with the left connector presoldered, with +* The Pluto-P board is shipped with the left connector presoldered, with the key in the indicated position. The other connectors are unpopulated. There does not seem to be a standard 12-pin IDC connector, but some of the pins of a 16P connector can hang off the board next to QA3/QZ3. - - The bottom and right connectors are on the same .1" grid, but the left +* The bottom and right connectors are on the same .1" grid, but the left connector is not. If OUT2…OUT9 are not required, a single IDC connector can span the bottom connector and the bottom two rows of the right connector. === Physical Pins - - Read the ACEX1K datasheet for information about input and output - voltage thresholds. The pins are all configured in "LVTTL/LVCMOS" mode +* Read the ACEX1K datasheet for information about input and output + voltage thresholds. The pins are all configured in 'LVTTL/LVCMOS' mode and are generally compatible with 5V TTL logic. - - Before configuration and after properly exiting EMC2, all Pluto-P pins +* Before configuration and after properly exiting EMC2, all Pluto-P pins are tristated with weak pull-ups (20k-ohms min, 50k-ohms max). If the watchdog timer is enabled (the default), these pins are also tristated after an interruption of communication between EMC2 and the board. The watchdog timer takes approximately 6.5ms to activate. However, software bugs in the pluto_servo firmware or EMC2 can leave the Pluto-P pins in an undefined state. - - In pwm+dir mode, by default dir is HIGH for negative values and LOW +* In pwm+dir mode, by default dir is HIGH for negative values and LOW for positive values. To select HIGH for positive values and LOW for negative values, set the corresponding dout-NN-invert parameter TRUE to invert the signal. - - The index input is triggered on the rising edge. Initial testing has +* The index input is triggered on the rising edge. Initial testing has shown that the QZx inputs are particularly noise sensitive, due to being polled every 25ns. Digital filtering has been added to filter pulses shorter than 175ns (seven polling times). Additional external filtering on all input pins, such as a Schmitt buffer or inverter, RC filter, or differential receiver (if applicable) is recommended. - - The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA +* The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA pins. No other pins have any sort of protection for out-of-spec voltages or currents. It is up to the integrator to add appropriate isolation and protection. Traditional parallel port optoisolator boards @@ -53,33 +56,33 @@ ACEX1K(((ACEX1K))) chip from Altera. === LED - - When the device is unprogrammed, the LED glows faintly. When the +* When the device is unprogrammed, the LED glows faintly. When the device is programmed, the LED glows according to the duty cycle of PWM0 - (*LED* = *UP0* 'xor' *DOWN0*) or STEPGEN0 (*LED* = *STEP0* 'xor' - *DIR0*). + ('LED' = 'UP0' 'xor' 'DOWN0') or STEPGEN0 ('LED' = 'STEP0' 'xor' + 'DIR0'). === Power - - A small amount of current may be drawn from VCC. The available current +* A small amount of current may be drawn from VCC. The available current depends on the unregulated DC input to the board. Alternately, regulated +3.3VDC may be supplied to the FPGA through these VCC pins. The required current is not yet known, but is probably around 50mA plus I/O current. - - The regulator on the Pluto-P board is a low-dropout type. Supplying 5V +* The regulator on the Pluto-P board is a low-dropout type. Supplying 5V at the power jack will allow the regulator to work properly. === PC interface - - Only a single pluto_servo or pluto_step board is supported. +* Only a single pluto_servo or pluto_step board is supported. === Rebuilding the FPGA firmware -The `src/hal/drivers/pluto_servo_firmware/` and -`src/hal/drivers/pluto_step_firmware/` subdirectories contain the +The 'src/hal/drivers/pluto_servo_firmware/' and +'src/hal/drivers/pluto_step_firmware/' subdirectories contain the Verilog source code plus additional files used by Quartus for the FPGA firmwares. Altera's Quartus II software is required to rebuild the FPGA firmware. To rebuild the firmware from the - .hdl and other source files, open the `.qpf` file and press CTRL-L. + .hdl and other source files, open the '.qpf' file and press CTRL-L. Then, recompile EMC2. Like the HAL hardware driver, the FPGA firmware is licensed under the @@ -103,33 +106,33 @@ limit switches. This driver features: - - 4 quadrature channels with 40MHz sample rate. The counters operate in - "4x" mode. The maximum useful quadrature rate is 8191 counts per EMC2 +* 4 quadrature channels with 40MHz sample rate. The counters operate in + '4x' mode. The maximum useful quadrature rate is 8191 counts per EMC2 servo cycle, or about 8MHz for EMC2's default 1ms servo rate. - - 4 PWM channels, "up/down" or "pwm+dir" style. 4095 duty cycles from +* 4 PWM channels, 'up/down' or 'pwm+dir' style. 4095 duty cycles from -100% to +100%, including 0%. The PWM period is approximately 19.5kHz (40MHz / 2047). A PDM-like mode is also available. - - 18 digital outputs: 10 dedicated, 8 shared with PWM functions. +* 18 digital outputs: 10 dedicated, 8 shared with PWM functions. (Example: A lathe with unidirectional PWM spindle control may use 13 total digital outputs) - - 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. +* 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. (Example: A lathe with index pulse only on the spindle may use 13 total digital inputs) - - EPP communication with the PC. The EPP communication typically takes +* EPP communication with the PC. The EPP communication typically takes around 100 us on machines tested so far, enabling servo rates above 1kHz. === Pinout UPx:: - The "up" (up/down mode) or “pwm” (pwm+direction mode) signal from PWM + The 'up' (up/down mode) or 'pwm' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is always negative. The corresponding digital output invert may be set to TRUE to make UPx active low rather than active high. DNx:: - The "down" (up/down mode) or “direction” (pwm+direction mode) signal + The 'down' (up/down mode) or 'direction' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is never negative. The corresponding digital ouput invert may be set to @@ -197,12 +200,12 @@ image::images/pluto-pinout.eps[] === Input latching and output updating - - PWM duty cycles for each channel are updated at different times. - - Digital outputs OUT0 through OUT9 are all updated at the same time. +* PWM duty cycles for each channel are updated at different times. +* Digital outputs OUT0 through OUT9 are all updated at the same time. Digital outputs OUT10 through OUT17 are updated at the same time as the pwm function they are shared with. - - Digital inputs IN0 through IN19 are all latched at the same time. - - Quadrature positions for each channel are latched at different times. +* Digital inputs IN0 through IN19 are all latched at the same time. +* Quadrature positions for each channel are latched at different times. === HAL Functions, Pins and Parameters @@ -231,19 +234,19 @@ limit switches. The board features: - - 4 “step+direction” channels with 312.5kHz maximum step rate, +* 4 'step+direction' channels with 312.5kHz maximum step rate, programmable step length, space, and direction change times - - 14 dedicated digital outputs - - 16 dedicated digital inputs - - EPP communication with the PC +* 14 dedicated digital outputs +* 16 dedicated digital inputs +* EPP communication with the PC === Pinout STEPx:: - The “step” (clock) output of stepgen channel *x* + The 'step' (clock) output of stepgen channel 'x' DIRx:: - The “direction” output of stepgen channel *x* + The 'direction' output of stepgen channel 'x' INx:: Dedicated digital input #x @@ -257,7 +260,7 @@ GND:: VCC:: +3.3V regulated DC -While the “extended main connector” has a superset of signals usually +While the 'extended main connector' has a superset of signals usually found on a Step & Direction DB25 connector--4 step generators, 9 inputs, and 6 general-purpose outputs--the layout on this header is different than the layout of a standard 26-pin ribbon cable to DB25 @@ -269,19 +272,19 @@ image::images/pluto-step-pinout.eps[] === Input latching and output updating - - Step frequencies for each channel are updated at different times. - - Digital outputs are all updated at the same time. - - Digital inputs are all latched at the same time. - - Feedback positions for each channel are latched at different times. +* Step frequencies for each channel are updated at different times. +* Digital outputs are all updated at the same time. +* Digital inputs are all latched at the same time. +* Feedback positions for each channel are latched at different times. === Step Waveform Timings The firmware and driver enforce step length, space, and direction change times. Timings are rounded up to the next multiple of -latexmath:[1.6μs], with a maximum of latexmath:[49.6μs]. The timings +1.6μs, with a maximum of 49.6μs. The timings are the same as for the software stepgen component, except that -“dirhold” and “dirsetup” have been merged into a single parameter -“dirtime” which should be the maximum of the two, and that the same +'dirhold' and 'dirsetup' have been merged into a single parameter +'dirtime' which should be the maximum of the two, and that the same step timings are always applied to all channels. .Pluto-Step Timings[[fig:Pluto-Step-Timings]](((pluto-step timings))) diff --git a/docs/src/drivers/pluto_p_es.txt b/docs/src/drivers/pluto_p_es.txt index 2d1bcf21a..20e0362b1 100644 --- a/docs/src/drivers/pluto_p_es.txt +++ b/docs/src/drivers/pluto_p_es.txt @@ -1,3 +1,6 @@ +:lang: es +:toc: + = Pluto-P == General Info @@ -7,44 +10,44 @@ ACEX1K(((ACEX1K))) chip from Altera. === Requirements - . A Pluto-P board - . An EPP-compatible parallel port, configured for EPP mode in the system BIOS +. A Pluto-P board +. An EPP-compatible parallel port, configured for EPP mode in the system BIOS === Connectors - - The Pluto-P board is shipped with the left connector presoldered, with +* The Pluto-P board is shipped with the left connector presoldered, with the key in the indicated position. The other connectors are unpopulated. There does not seem to be a standard 12-pin IDC connector, but some of the pins of a 16P connector can hang off the board next to QA3/QZ3. - - The bottom and right connectors are on the same .1" grid, but the left +* The bottom and right connectors are on the same .1" grid, but the left connector is not. If OUT2…OUT9 are not required, a single IDC connector can span the bottom connector and the bottom two rows of the right connector. === Physical Pins - - Read the ACEX1K datasheet for information about input and output - voltage thresholds. The pins are all configured in "LVTTL/LVCMOS" mode +* Read the ACEX1K datasheet for information about input and output + voltage thresholds. The pins are all configured in 'LVTTL/LVCMOS' mode and are generally compatible with 5V TTL logic. - - Before configuration and after properly exiting EMC2, all Pluto-P pins +* Before configuration and after properly exiting EMC2, all Pluto-P pins are tristated with weak pull-ups (20k-ohms min, 50k-ohms max). If the watchdog timer is enabled (the default), these pins are also tristated after an interruption of communication between EMC2 and the board. The watchdog timer takes approximately 6.5ms to activate. However, software bugs in the pluto_servo firmware or EMC2 can leave the Pluto-P pins in an undefined state. - - In pwm+dir mode, by default dir is HIGH for negative values and LOW +* In pwm+dir mode, by default dir is HIGH for negative values and LOW for positive values. To select HIGH for positive values and LOW for negative values, set the corresponding dout-NN-invert parameter TRUE to invert the signal. - - The index input is triggered on the rising edge. Initial testing has +* The index input is triggered on the rising edge. Initial testing has shown that the QZx inputs are particularly noise sensitive, due to being polled every 25ns. Digital filtering has been added to filter pulses shorter than 175ns (seven polling times). Additional external filtering on all input pins, such as a Schmitt buffer or inverter, RC filter, or differential receiver (if applicable) is recommended. - - The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA +* The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA pins. No other pins have any sort of protection for out-of-spec voltages or currents. It is up to the integrator to add appropriate isolation and protection. Traditional parallel port optoisolator boards @@ -53,33 +56,33 @@ ACEX1K(((ACEX1K))) chip from Altera. === LED - - When the device is unprogrammed, the LED glows faintly. When the +* When the device is unprogrammed, the LED glows faintly. When the device is programmed, the LED glows according to the duty cycle of PWM0 - (*LED* = *UP0* 'xor' *DOWN0*) or STEPGEN0 (*LED* = *STEP0* 'xor' - *DIR0*). + ('LED' = 'UP0' 'xor' 'DOWN0') or STEPGEN0 ('LED' = 'STEP0' 'xor' + 'DIR0'). === Power - - A small amount of current may be drawn from VCC. The available current +* A small amount of current may be drawn from VCC. The available current depends on the unregulated DC input to the board. Alternately, regulated +3.3VDC may be supplied to the FPGA through these VCC pins. The required current is not yet known, but is probably around 50mA plus I/O current. - - The regulator on the Pluto-P board is a low-dropout type. Supplying 5V +* The regulator on the Pluto-P board is a low-dropout type. Supplying 5V at the power jack will allow the regulator to work properly. === PC interface - - Only a single pluto_servo or pluto_step board is supported. +* Only a single pluto_servo or pluto_step board is supported. === Rebuilding the FPGA firmware -The `src/hal/drivers/pluto_servo_firmware/` and -`src/hal/drivers/pluto_step_firmware/` subdirectories contain the +The 'src/hal/drivers/pluto_servo_firmware/' and +'src/hal/drivers/pluto_step_firmware/' subdirectories contain the Verilog source code plus additional files used by Quartus for the FPGA firmwares. Altera's Quartus II software is required to rebuild the FPGA firmware. To rebuild the firmware from the - .hdl and other source files, open the `.qpf` file and press CTRL-L. + .hdl and other source files, open the '.qpf' file and press CTRL-L. Then, recompile EMC2. Like the HAL hardware driver, the FPGA firmware is licensed under the @@ -103,33 +106,33 @@ limit switches. This driver features: - - 4 quadrature channels with 40MHz sample rate. The counters operate in - "4x" mode. The maximum useful quadrature rate is 8191 counts per EMC2 +* 4 quadrature channels with 40MHz sample rate. The counters operate in + '4x' mode. The maximum useful quadrature rate is 8191 counts per EMC2 servo cycle, or about 8MHz for EMC2's default 1ms servo rate. - - 4 PWM channels, "up/down" or "pwm+dir" style. 4095 duty cycles from +* 4 PWM channels, 'up/down' or 'pwm+dir' style. 4095 duty cycles from -100% to +100%, including 0%. The PWM period is approximately 19.5kHz (40MHz / 2047). A PDM-like mode is also available. - - 18 digital outputs: 10 dedicated, 8 shared with PWM functions. +* 18 digital outputs: 10 dedicated, 8 shared with PWM functions. (Example: A lathe with unidirectional PWM spindle control may use 13 total digital outputs) - - 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. +* 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. (Example: A lathe with index pulse only on the spindle may use 13 total digital inputs) - - EPP communication with the PC. The EPP communication typically takes +* EPP communication with the PC. The EPP communication typically takes around 100 us on machines tested so far, enabling servo rates above 1kHz. === Pinout UPx:: - The "up" (up/down mode) or “pwm” (pwm+direction mode) signal from PWM + The 'up' (up/down mode) or 'pwm' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is always negative. The corresponding digital output invert may be set to TRUE to make UPx active low rather than active high. DNx:: - The "down" (up/down mode) or “direction” (pwm+direction mode) signal + The 'down' (up/down mode) or 'direction' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is never negative. The corresponding digital ouput invert may be set to @@ -197,12 +200,12 @@ image::images/pluto-pinout.eps[] === Input latching and output updating - - PWM duty cycles for each channel are updated at different times. - - Digital outputs OUT0 through OUT9 are all updated at the same time. +* PWM duty cycles for each channel are updated at different times. +* Digital outputs OUT0 through OUT9 are all updated at the same time. Digital outputs OUT10 through OUT17 are updated at the same time as the pwm function they are shared with. - - Digital inputs IN0 through IN19 are all latched at the same time. - - Quadrature positions for each channel are latched at different times. +* Digital inputs IN0 through IN19 are all latched at the same time. +* Quadrature positions for each channel are latched at different times. === HAL Functions, Pins and Parameters @@ -231,19 +234,19 @@ limit switches. The board features: - - 4 “step+direction” channels with 312.5kHz maximum step rate, +* 4 'step+direction' channels with 312.5kHz maximum step rate, programmable step length, space, and direction change times - - 14 dedicated digital outputs - - 16 dedicated digital inputs - - EPP communication with the PC +* 14 dedicated digital outputs +* 16 dedicated digital inputs +* EPP communication with the PC === Pinout STEPx:: - The “step” (clock) output of stepgen channel *x* + The 'step' (clock) output of stepgen channel 'x' DIRx:: - The “direction” output of stepgen channel *x* + The 'direction' output of stepgen channel 'x' INx:: Dedicated digital input #x @@ -257,7 +260,7 @@ GND:: VCC:: +3.3V regulated DC -While the “extended main connector” has a superset of signals usually +While the 'extended main connector' has a superset of signals usually found on a Step & Direction DB25 connector--4 step generators, 9 inputs, and 6 general-purpose outputs--the layout on this header is different than the layout of a standard 26-pin ribbon cable to DB25 @@ -269,19 +272,19 @@ image::images/pluto-step-pinout.eps[] === Input latching and output updating - - Step frequencies for each channel are updated at different times. - - Digital outputs are all updated at the same time. - - Digital inputs are all latched at the same time. - - Feedback positions for each channel are latched at different times. +* Step frequencies for each channel are updated at different times. +* Digital outputs are all updated at the same time. +* Digital inputs are all latched at the same time. +* Feedback positions for each channel are latched at different times. === Step Waveform Timings The firmware and driver enforce step length, space, and direction change times. Timings are rounded up to the next multiple of -latexmath:[1.6μs], with a maximum of latexmath:[49.6μs]. The timings +1.6μs, with a maximum of 49.6μs. The timings are the same as for the software stepgen component, except that -“dirhold” and “dirsetup” have been merged into a single parameter -“dirtime” which should be the maximum of the two, and that the same +'dirhold' and 'dirsetup' have been merged into a single parameter +'dirtime' which should be the maximum of the two, and that the same step timings are always applied to all channels. .Pluto-Step Timings[[fig:Pluto-Step-Timings]](((pluto-step timings))) diff --git a/docs/src/drivers/pluto_p_pl.txt b/docs/src/drivers/pluto_p_pl.txt index 2d1bcf21a..4cf84ddd7 100644 --- a/docs/src/drivers/pluto_p_pl.txt +++ b/docs/src/drivers/pluto_p_pl.txt @@ -1,3 +1,5 @@ +:toc: + = Pluto-P == General Info @@ -7,44 +9,44 @@ ACEX1K(((ACEX1K))) chip from Altera. === Requirements - . A Pluto-P board - . An EPP-compatible parallel port, configured for EPP mode in the system BIOS +. A Pluto-P board +. An EPP-compatible parallel port, configured for EPP mode in the system BIOS === Connectors - - The Pluto-P board is shipped with the left connector presoldered, with +* The Pluto-P board is shipped with the left connector presoldered, with the key in the indicated position. The other connectors are unpopulated. There does not seem to be a standard 12-pin IDC connector, but some of the pins of a 16P connector can hang off the board next to QA3/QZ3. - - The bottom and right connectors are on the same .1" grid, but the left +* The bottom and right connectors are on the same .1" grid, but the left connector is not. If OUT2…OUT9 are not required, a single IDC connector can span the bottom connector and the bottom two rows of the right connector. === Physical Pins - - Read the ACEX1K datasheet for information about input and output - voltage thresholds. The pins are all configured in "LVTTL/LVCMOS" mode +* Read the ACEX1K datasheet for information about input and output + voltage thresholds. The pins are all configured in 'LVTTL/LVCMOS' mode and are generally compatible with 5V TTL logic. - - Before configuration and after properly exiting EMC2, all Pluto-P pins +* Before configuration and after properly exiting EMC2, all Pluto-P pins are tristated with weak pull-ups (20k-ohms min, 50k-ohms max). If the watchdog timer is enabled (the default), these pins are also tristated after an interruption of communication between EMC2 and the board. The watchdog timer takes approximately 6.5ms to activate. However, software bugs in the pluto_servo firmware or EMC2 can leave the Pluto-P pins in an undefined state. - - In pwm+dir mode, by default dir is HIGH for negative values and LOW +* In pwm+dir mode, by default dir is HIGH for negative values and LOW for positive values. To select HIGH for positive values and LOW for negative values, set the corresponding dout-NN-invert parameter TRUE to invert the signal. - - The index input is triggered on the rising edge. Initial testing has +* The index input is triggered on the rising edge. Initial testing has shown that the QZx inputs are particularly noise sensitive, due to being polled every 25ns. Digital filtering has been added to filter pulses shorter than 175ns (seven polling times). Additional external filtering on all input pins, such as a Schmitt buffer or inverter, RC filter, or differential receiver (if applicable) is recommended. - - The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA +* The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA pins. No other pins have any sort of protection for out-of-spec voltages or currents. It is up to the integrator to add appropriate isolation and protection. Traditional parallel port optoisolator boards @@ -53,33 +55,33 @@ ACEX1K(((ACEX1K))) chip from Altera. === LED - - When the device is unprogrammed, the LED glows faintly. When the +* When the device is unprogrammed, the LED glows faintly. When the device is programmed, the LED glows according to the duty cycle of PWM0 - (*LED* = *UP0* 'xor' *DOWN0*) or STEPGEN0 (*LED* = *STEP0* 'xor' - *DIR0*). + ('LED' = 'UP0' 'xor' 'DOWN0') or STEPGEN0 ('LED' = 'STEP0' 'xor' + 'DIR0'). === Power - - A small amount of current may be drawn from VCC. The available current +* A small amount of current may be drawn from VCC. The available current depends on the unregulated DC input to the board. Alternately, regulated +3.3VDC may be supplied to the FPGA through these VCC pins. The required current is not yet known, but is probably around 50mA plus I/O current. - - The regulator on the Pluto-P board is a low-dropout type. Supplying 5V +* The regulator on the Pluto-P board is a low-dropout type. Supplying 5V at the power jack will allow the regulator to work properly. === PC interface - - Only a single pluto_servo or pluto_step board is supported. +* Only a single pluto_servo or pluto_step board is supported. === Rebuilding the FPGA firmware -The `src/hal/drivers/pluto_servo_firmware/` and -`src/hal/drivers/pluto_step_firmware/` subdirectories contain the +The 'src/hal/drivers/pluto_servo_firmware/' and +'src/hal/drivers/pluto_step_firmware/' subdirectories contain the Verilog source code plus additional files used by Quartus for the FPGA firmwares. Altera's Quartus II software is required to rebuild the FPGA firmware. To rebuild the firmware from the - .hdl and other source files, open the `.qpf` file and press CTRL-L. + .hdl and other source files, open the '.qpf' file and press CTRL-L. Then, recompile EMC2. Like the HAL hardware driver, the FPGA firmware is licensed under the @@ -103,33 +105,33 @@ limit switches. This driver features: - - 4 quadrature channels with 40MHz sample rate. The counters operate in - "4x" mode. The maximum useful quadrature rate is 8191 counts per EMC2 +* 4 quadrature channels with 40MHz sample rate. The counters operate in + '4x' mode. The maximum useful quadrature rate is 8191 counts per EMC2 servo cycle, or about 8MHz for EMC2's default 1ms servo rate. - - 4 PWM channels, "up/down" or "pwm+dir" style. 4095 duty cycles from +* 4 PWM channels, 'up/down' or 'pwm+dir' style. 4095 duty cycles from -100% to +100%, including 0%. The PWM period is approximately 19.5kHz (40MHz / 2047). A PDM-like mode is also available. - - 18 digital outputs: 10 dedicated, 8 shared with PWM functions. +* 18 digital outputs: 10 dedicated, 8 shared with PWM functions. (Example: A lathe with unidirectional PWM spindle control may use 13 total digital outputs) - - 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. +* 20 digital inputs: 8 dedicated, 12 shared with Quadrature functions. (Example: A lathe with index pulse only on the spindle may use 13 total digital inputs) - - EPP communication with the PC. The EPP communication typically takes +* EPP communication with the PC. The EPP communication typically takes around 100 us on machines tested so far, enabling servo rates above 1kHz. === Pinout UPx:: - The "up" (up/down mode) or “pwm” (pwm+direction mode) signal from PWM + The 'up' (up/down mode) or 'pwm' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is always negative. The corresponding digital output invert may be set to TRUE to make UPx active low rather than active high. DNx:: - The "down" (up/down mode) or “direction” (pwm+direction mode) signal + The 'down' (up/down mode) or 'direction' (pwm+direction mode) signal from PWM generator X. May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is never negative. The corresponding digital ouput invert may be set to @@ -197,12 +199,12 @@ image::images/pluto-pinout.eps[] === Input latching and output updating - - PWM duty cycles for each channel are updated at different times. - - Digital outputs OUT0 through OUT9 are all updated at the same time. +* PWM duty cycles for each channel are updated at different times. +* Digital outputs OUT0 through OUT9 are all updated at the same time. Digital outputs OUT10 through OUT17 are updated at the same time as the pwm function they are shared with. - - Digital inputs IN0 through IN19 are all latched at the same time. - - Quadrature positions for each channel are latched at different times. +* Digital inputs IN0 through IN19 are all latched at the same time. +* Quadrature positions for each channel are latched at different times. === HAL Functions, Pins and Parameters @@ -231,19 +233,19 @@ limit switches. The board features: - - 4 “step+direction” channels with 312.5kHz maximum step rate, +* 4 'step+direction' channels with 312.5kHz maximum step rate, programmable step length, space, and direction change times - - 14 dedicated digital outputs - - 16 dedicated digital inputs - - EPP communication with the PC +* 14 dedicated digital outputs +* 16 dedicated digital inputs +* EPP communication with the PC === Pinout STEPx:: - The “step” (clock) output of stepgen channel *x* + The 'step' (clock) output of stepgen channel 'x' DIRx:: - The “direction” output of stepgen channel *x* + The 'direction' output of stepgen channel 'x' INx:: Dedicated digital input #x @@ -257,7 +259,7 @@ GND:: VCC:: +3.3V regulated DC -While the “extended main connector” has a superset of signals usually +While the 'extended main connector' has a superset of signals usually found on a Step & Direction DB25 connector--4 step generators, 9 inputs, and 6 general-purpose outputs--the layout on this header is different than the layout of a standard 26-pin ribbon cable to DB25 @@ -269,19 +271,19 @@ image::images/pluto-step-pinout.eps[] === Input latching and output updating - - Step frequencies for each channel are updated at different times. - - Digital outputs are all updated at the same time. - - Digital inputs are all latched at the same time. - - Feedback positions for each channel are latched at different times. +* Step frequencies for each channel are updated at different times. +* Digital outputs are all updated at the same time. +* Digital inputs are all latched at the same time. +* Feedback positions for each channel are latched at different times. === Step Waveform Timings The firmware and driver enforce step length, space, and direction change times. Timings are rounded up to the next multiple of -latexmath:[1.6μs], with a maximum of latexmath:[49.6μs]. The timings +1.6μs, with a maximum of 49.6μs. The timings are the same as for the software stepgen component, except that -“dirhold” and “dirsetup” have been merged into a single parameter -“dirtime” which should be the maximum of the two, and that the same +'dirhold' and 'dirsetup' have been merged into a single parameter +'dirtime' which should be the maximum of the two, and that the same step timings are always applied to all channels. .Pluto-Step Timings[[fig:Pluto-Step-Timings]](((pluto-step timings))) |
