Designing the chips themselves, rather building things out of chips.
updated 2003-02-08
This page is about designing things are being built today; see also nanotechnology for some thoughts about the ultimate future and limits of MEMS -- things that seem likely to be designed within another lifetime.
This file contains pointers to vlsi design guides and software.
includes:
David also maintains related files:
I'm thinking about moving this whole page to a wiki. I found on VLSI wiki for a particular class. Is there a better wiki for VLSI stuff ?
Typically the electronics part of a system is partitioned into 4 parts, with no 2 parts residing on the same chip.
Anything that could be implemented at one level of this list can also be implemented at higher levels; but generally, when you have large numbers of something you want to do, and these things don't really require the ultimate in speed/power, it's far cheaper to migrate those functions to a lower level on this list, because these things are so regular you can generally find off-the-shelf chips that already to that. On the other hand, when you want a system to go faster, you typically find the bottleneck in the system (a few locations of slow memory, a few parts of the datapath, a few common sequences of the control logic) and move them to a higher level. (at the start of 1998, the bottleneck in most desktop CPUs was slow virtual memory; adding more DRAM had the best performance_increase/cost ratio).
A typical system has far more "stuff" (countable things) at lower levels of this list than at higher levels (even though they may sometimes have roughly equivalent physical areas, since the regular structures lower on the list can pack together much more tightly).
Once upon a time the (3) and (4) were always partitioned into separate chips; now it's invariably stuck all in one chip (CPU, MPU, DSP); sometimes we see 2 chips in a system that both have mixtures of this (a CPU and a FPGA).
The trend continues to try to keep merging consecutive levels on a single chip. For example,
The ultimate extension of this trend is, of course, to merge all functions all on one chip -- "systems-on-a-chip". In fact, some of the most interesting "chips" out there try to add mechanical and chemical functionality to a chip -- -- this is generally called MEMS.
On the other hand, the memory levels (5 and 6) seem to keep diversifying -- -- many of the fastest systems have a "multi-level memory architecture" with 4 different levels of memory -- "Virtual memory" on magnetic media, "physical memory" in DRAM, L2 cache in SRAM, and L1 cache integrated on the CPU.
Layout editors and related tools for chip design (control logic and datapath logic); papers about the design process.
The most famous is the freeware Magic.
The general types / categories of design tools for designing either very large scale integrated (VLSI) devices or printed wiring board (PWB).
Date: Mon, 25 Oct 1999 16:09:51 +0200 From: Magnus Danielson <magda at netinsight.se> X-Accept-Language: en To: geda-dev at geda.seul.org Subject: gEDA: Reading for thus interested in ASIC stuff Sender: owner-geda-dev at geda.seul.org Reply-To: geda-dev at geda.seul.org Hi! For those not aware of it, Steven Rubin has put his book "Computer Aids for VLSI Design" up on the web. You will find it at: http://www.rulabinsky.com/cavd/ While this book migth be sligthly outdated I think it could serve as an interesting reading. Notice the Appendix that covers CIF, GDS II etc. Steve Rubin is also singer in Severe Tire Damage (http://www.std.org), a band that we all know too well ;) Going even further off-topic, another of the band members, Mark Manasse, who plays bass and sings, is known do LARGE prime tests like when he found the 9:th Fermat number. Cheers, Magnus
Specific Software
http://kristopherjohnson.net/cgi-bin/twiki/view/Main seems to be the place for the latest information on colorForth http://www.colorforth.com/ .
VLSI designs: some specific implementations.
photographs of chips
Also libraries that might come in useful for your design.
[FIXME: I thought I had lots of links to pictures of various low power designs....]
see also
...
the end of idle loops as timing devices
-- Tom Engibous Chairman, President & Chief Executive Officer Texas Instruments Incorporated 2001 BusinessWeek Telecom Summit: Broadband Connections April 27, 2001 - Dallas http://www.ti.com/corp/docs/investor/speeches/bizweek01/index.shtml (DAV: according to these (rough) numbers, the 1980 chip pulled a total of 1.25 A, while the 2001 chip pulled a total of 0.5 A, at full speed. Full speed MIPs multiplied by 1000, while power per MIP was divided by 2 500 .)...
Today, the law that says the number of transistors on a chip will double every 18 months has to share the driver's seat with Gene's Law on energy consumption.
Gene Frantz is the TI Senior Fellow who postulated that the energy requirements to run a chip will drop by a factor of 1.6 every year.
... In 1980, one of TI's typical DSP chips had 50,000 transistors and could process 5 million instructions per second -- or MIPS.
These chips sold for about $150 each and consumed 250 milliwatts of power per MIP.
Today, we routinely put 5 million transistors on a chip -- and we deliver 5 billion instructions per second at just one-tenth of a milliwatt per MIP. We can sell this chip for about $5.
That's less than a penny per MIP compared to $30 per MIP 20 years ago. And power consumption is a tiny sliver of what it once was.
By 2010, we anticipate DSPs that can process 3 trillion instructions per second with a chip about the size of a thumbtack.
...
"If extending the battery life is the only concern, then the energy (that is, the power*delay product) should be minimized ... battery consumption is minimized even though an operation may take a very long time. On the other hand, if both the battery life and circuit delay are important ... energy*delay product ... [or] In most scenarios, the circuit delay is set based on system-level considerations, and hence during circuit optimization, one minimizes power under user-specified timing constraints."
"Interconnect plays an increasing role in determining the total chip area, delay, and power dissipation"
"A Gray code addressing scheme can be used to reduce the number of bit changes on the address bus"
TI Introduces MSP430 Microcontroller Family for Electronic Energy Meteringarticle (press release ?) by Janell Mirochna, Texas Instruments, Jul 31, 2003 http://microcontroller.com/news/ti_MSP430FE42x.asp
ultra-low-power Flash MCU with an integrated high-performance analog front-end (AFE) on a single-chip, the mixed-signal integration of the new MSP430FE42x family of products ...
... the device integrates ...
- Three independent 16-bit sigma-delta analog-to-digital converters operating at an oversampled rate of 1MHz
- Three programmable gain amplifiers
- Temperature sensor
- Precision voltage reference
The converted line voltage and current signals ... precise phase matching between current and voltage channels ...
The MSP430FE42x operates at 3V with the CPU and ESP active at only 2.5mA. In a power outage the device can operate in a standby mode with a typical current consumption of 1.1uA with the real-time-clock active.
... The 8kB MSP430FE423 is priced at $2.95 per unit in 100,000-piece quantities.
David Cary has a subscription to the _Journal of Microelectromechanical Systems: A Joint IEEE and ASME Publication on Microstructures, Microactuators, Microsensors, and Microsystems_ . This journal has lots of scanning-electron-microscope (SEM) photographs of actual MEMS.
Mems links:
DENSO researchers succeeded in 1996 in eliminating the energy source copper wire that powered its 1995 Micro-Car.
The 1996 model has no wire at all. Instead, it receives its power through remote magnetic energy transmission.
... researcher Dr. Tadashi Hattori of DENSO Research Laboratories in Nisshin, Japan.
Hattori explains, "A wireless, micro-robot would be able to travel where human beings could not. ... through veins or arteries to treat defects without major sugery."
clockless logic and the metastable state.
"NULL Convention Logic(TM) (NCL)(TM) ", a kind of "clockless logic", "self-timed logic", a alternative to "Clocked Boolean Logic (CBL)." Can be used in standard FPGAs. Because it doesn't need clocks, it promises to reduce power consumption.
Unfortunately, "the metastable state is the bane of asynchronous digital systems." A good explanation of the (surprising) problems this causes in asynchronous circuits (and why it is not a problem in clocked circuits) is in the book _Computation Structures_ by Ward and Halstead (section 4.6).
the metastable state
Subject:
Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
Date:
10 Jan 1999 00:00:00 GMT
From:
Wen-King Su
Organization:
Myricom Inc.
Newsgroups:
comp.arch.fpga, sci.electronics.design
References:
1
In a previous article "Frank Bemelman" writes:
:
:Still, I don't think I am irresponsible. I am not designing
;medical life support systems. I do not design stuff for
:airplanes. I dont know anything about satellite and
;spaceships. But I do know my designs are more than adequate
:for their purposes.
While metastability can't be completely eliminated, it can be completely
compartmentalized to the extent that it is of no concern to most designers.
The issue can be restricted to a thin boundary in the part of the circuit
that interfaces differing clock domains or between a clocked domain and
an asynchronous domain. Techniques exists to arbitrarily reduce the
probability of meta-stable state propogating into the core of the circuit.
It can be done so at the expense of latency without giving up bandwidth.
Subject:
Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
Date:
11 Jan 1999 00:00:00 GMT
From:
"Bruce Nepple"
Organization:
ISPNews http://ispnews.com
Newsgroups:
comp.arch.fpga, sci.electronics.design
References:
1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9
I have pretty strong opinions about this. Hopefully when you read this you
will try to understand my points, not pick apart my choice of words:
1. If you are a digital designer and you do not understand metastability,
you cannot do reliable digital design (except by luck, or as a synchronous
subsystem only)
2. If you do not understand exactly what metastable behavior will do to
your design, your design should be considered "unsafe" in that it *might* do
something unpredictable.
3. If you understand how often you design might fail due to metastability,
and the nature of the failure, and you are satisfied with it, you have done
your job.
>Fact is, I am designing relatively simple uP boards. I even
>have to write the software for it. My designs aren't 100%
>reliable, mostly because I haven't removed all software
>flaws yet. I can understand that one can get excited about
>metastability, but *I* couldn't care less. The article I
>have read, showed an example where an improvement was
>suggested, putting 2 d-flipflops in cascade, resulting in 1
>occurence of metastability once every 2 million years.
>Although very interesting, I am not even considering that
>advice for my future designs, because I like to see this
>metastability-thing at least once in my life.
>
What was the failure rate *before* the second flip flop was added? The
whole point is that the second flip-flop makes the failure rate tolerable
(in most situations). My rule of thumb is that if the metastable failure
rate is better that the failure rate for the worst part in the system, then
I'm in the right ballpark. If your software crashes once a week, (and you
work for Microsoft so that is OK with you <g>), then your metastable
requirements have opened up nicely.
The important point is that every digital designer *must* consider
metastability in the context in which the design is being done. It should
never be totally overlooked.
bruce
"Having spent untold hours at analyzing and measuring metastable
behavior, I can assure you that it is (today) a highly overrated
problem. You can almost ignore it."
Peter Alfke
12/28/98
"Having spend untold hours debugging digital designs, I can assure you that
metastable behavior is a real problem, and every digital designer had better
understand it"
Bruce Nepple
12/31/98
Subject:
Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
Date:
31 Dec 1998 00:00:00 GMT
From:
"Bruce Nepple"
Organization:
ISPNews http://ispnews.com
Newsgroups:
comp.arch.fpga, sci.electronics.design
References:
1 , 2
I once ran some experiments on 74S74 flip flops to determine the extent of
their metastable behavior. There was some difference from vendor to vendor
and part to part, but it was worthwhile to characterize what might be a
reasonable settling time. If you have the time, it would be educational to
duplicate what I did. I essentially built a 2 stage synchronizer with
clocks driven from two identical Schmidt triggers. The input to one of the
schmitt triggers was delayed slightly by an RC network (variable R, small
C). The delayed circuit drove the second flop. I could adjust the R until
I saw unstable behavior on the output of the second flip flop. (the first
flop should be connected to toggle).
osc ----schmitt ----schmitt ----first flop clock
|--schmitt--RC--schmitt ----second flop clock
Still have some pretty neat pictures of flip flop outputs pulsing high then
low after the clock. It was amazing how accurately I needed to adjust the
delay. I expect it will be even harder now-a-days. Also, the difference
between low to high D and high to low D was dramatic.
Bruce
.extra blows away the email
--------------- design -----------
Subject:
Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
Date:
06 Jan 1999 00:00:00 GMT
From:
murray at pa.dec.com (Hal Murray)
Organization:
Compaq Systems Research Center
Newsgroups:
comp.arch.fpga, sci.electronics.design
References:
1 , 2 , 3 , 4 , 5 , 6 , 7
In article <S4WnzrBY0ok2EwBJ@jmwa.demon.co.uk>, John Woodgate <jmw at jmwa.demon.co.uk> writes:
> <76sf7q$1ip@src-news.pa.dec.com>, Hal Murray <murray at pa.dec.com> wrote:
> >If the problem is "irrelevant" for "most applications", how do I tell
> >if I'm working on one where it is relevant?
>
> Assume that it is, until you prove that it isn't. In other words, if it
> works, OK; if it doesn't, don't rule out metastability as the cause.
That's the sort of attitude that gets people burned. Testing
a design doesn't tell you it doesn't have any metastability problems.
It only tells you that they don't happen often enough for your
tests to catch them.
Suppose you design a disk controller. You test it hard for a week.
It works great. So you test 10 of them for a month. No troubles.
So you ship it.
Suppose it has a once-a-year metastability bug that trashes your data.
Your testing only has a 50-50 chance of finding one. Maybe you missed it.
Most systems don't run the disk as hard as test programs do but
some machines are pretty busy. So every 10 years you get some
data trashed. If you have a dozen machines that means an obscure
bug/glitch every year or so. If you are running crappy software nobody
will notice a quirk a year. But not all software is crappy. Some of
us expect disk subsystems and operating systems to work - or at least
not trash our data without some hint. Once a year type bugs are a real
pain to track down.
You can't test out metastability! You have to understand things
and do it right at design time.
--
These are my opinions, not necessarily my employers.
Subject:
Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
Date:
06 Jan 1999 00:00:00 GMT
From:
rk <stellare@NOSPAMerols.com>
Organization:
sel
To:
John Woodgate <jmw at jmwa.demon.co.uk>
Newsgroups:
comp.arch.fpga, sci.electronics.design
References:
1 , 2 , 3 , 4 , 5 , 6 , 7
John Woodgate wrote:
> <76sf7q$1ip@src-news.pa.dec.com>, Hal Murray <murray at pa.dec.com> wrote:
> >If the problem is "irrelevant" for "most applications", how do I tell
> >if I'm working on one where it is relevant?
>
> Assume that it is, until you prove that it isn't. In other words, if it
> works, OK; if it doesn't, don't rule out metastability as the cause.
ah, the russian roullette [spell] theory of electronics design.
if you take your parameters and analyze the failure rate as a result of
metastability, then you will see it's a pretty small number, if the system is
properly designed, which includes timing margin to resolve flip-flops that have
gone metastable. this makes a "qualification by test" somewhat, well,
impractical.
poorly designed systems may not have enough margin [getting tougher, as the times
are getting to be quite small] but worse bad design practices can leave you
further exposed to metastable [or logic hazard or whatever] problems.. so, how
do you tell if it works? run it in the lab for a day? over a weekend? for a
week? for a months? if you have to design systems that run interrupted for,
say, 15 years, and it's a critical system - it better not fail. what do you do?
and when you test it, how do you know if you get the right combination of
parameters? i've been called in to debug systems that were designed for YEARS
and then had a failure, frequently blamed on parts or phase of the moon.
virtually everytime it was a design defect that was not detectable by just
sticking it on a bench and running it. or even cooking it in the oven and moving
the voltage up and down.
independent of what the design flaw is, assuming that a circuit is good until
proven guilty is really a crime against humanity and you shouldn't really have
anything to do with electronics, in my opinion. in practice, one should follow
barto's law: EVERY CIRCUIT IS CONSIDERED GUILTY UNTIL PROVEN INNOCENT!
damn, another reason to have the little red buttons on the front of electronic
boxes,
rk
p.s. sorry 'bout the rant, but people read this stuff, this junk needs to be
stepped on, HARD!
==================================
> --
> Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124.
> OOO - Own Opinions Only. You can fool all of the people some of the time, but
> you can't please some of the people any of the time.
Subject:
Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
Date:
06 Jan 1999 00:00:00 GMT
From:
John Woodgate <jmw at jmwa.demon.co.uk>
Organization:
JMWA Electronics Consultancy
Newsgroups:
comp.arch.fpga, sci.electronics.design
References:
1 , 2 , 3 , 4 , 5 , 6 , 7 , 8
<36934FF2.234F64BD@NOSPAMerols.com>, rk <stellare@NOSPAMerols.com>
wrote, preferably NOT having sent me a copy by e-mail:
>ah, the russian roullette [spell] theory of electronics design.
See my reply in this thread to a much politer critique of what I wrote.
You don't have to be insulting to make your point. In fact, the more you
bluster, the less strong your case seems.
I've survived in electronics for 43 years, and so have my designs: AFAIK
none has failed seriously. It's a bit late for a career change now.
--
Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124.
OOO - Own Opinions Only. You can fool all of the people some of the time, but
you can't please some of the people any of the time.
--------------- /design -----------
technical notes and future trends (woefully incomplete)
This list mostly focuses on timing diagrams and ways to interface to commodity memory devices. Currently "EDO DRAM" is the most common memory interface. "FLASH RAM" is becoming popular for handheld devices.
see also Writing Device Drivers for some PCI-related software tools.
see also serialportdocs.html for lots of other communication buses including USB.
see also Universal Plug and Play http://www.upnp.org/ .
General Information about PCI:
From: "O'Shea, David J" < david.j.oshea at intel.com > To: pci-sig at znyx.com Subject: RE: Device at address 0 Date: Mon, 5 Aug 2002 10:10:05 -0700
...
Zero base addresses are LEGAL! If your device cannot accomadate a zero base address, its designed improperly. Most devices on the market are likely designed improperly.
...
Truthfully, on some custom IA system designs, one want to assign a PCI device to address 0, if that device hosted memory. Or for debugging purposes, again a "custom" system BIOS might want to assign a zero address.
In general, people should follow the specification, which specifies that all addresses are legal (including 0), and that enable/disable is controlled by the "command" register, using the I/O and memory space enable bits. That is not only what the specification actually says, it is what was intended by the specification.
The specification is multi-architecture friendly, and it is intended and written such that zero as a base address register assignment is LEGAL!
-David O'Shea Intel Corp.
I would bet that the authors of the PCI Specification decidely did not use the term "DMA," instead using the terms initiator, target, master, and slave specifically to avoid confusion with ISA DMA.-- From: Lame Brooks-G14738 <brooks.lame at motorola.com> Date: Thu, 14 Dec 2000 18:07:13 -0800
J. J. Farrell 2001-12-14 responded:
Very likely. PCI was defined with PCs very much in mind, and with PCs
as the main target application. The PC has a tendency to grab widely
used industry terms, and corrupt and bend them to fit into its own
little twisted world - consider "windows" for example. PCI mastering
to "main" memory by any device other than a CPU is "DMA" in its proper
sense. When much of the target audience has been mislead into thinking
that "DMA" refers explicitly to some kludge on a PC, an author is wise
to avoid using the term at all since it will probably confuse somebody.
--
Date: Thu, 14 Dec 2000 19:31:00 -0800 (PST)
From: "J. J. Farrell" <jjf at bcs.org.uk>
2.9 Where can I find bus specs and interfacing information?
...
* ISA, EISA, VLB, and PCI pinouts, signal descriptions, and timing
information can be found at http://users.desupernet.com/sokos/PAGE2.HTM
...
* The PCI specification may be obtained from: PCI Special Interest Group
(SIG) P.O. Box 14070, Portland, OR 97214
(800) 433-5177 (503) 797-4207 FAX: 234-6762 (503) 797 4297
http://www.pcisig.com/ * Other PCI information:
o http://www.teleport.com/~pc2/pcisigindex.html
o http://www.vchips.com/products/pcicores.htm
o http://www.altera.com/html/new/pressrel.old/pr_pcipack.html
o http://www.cypress.com/cypressprodgate/apps/ultralogic.html
o http://www.xilinx.com/apps/pci.htm
o ftp://fission.dt.wdc.com/pub/otherdocs/pc_systems/how_it_works
* AMCC makes a chip which provides an interface to PCI on one side and a
fairly simple generic interface on the other side. AMCC is in San
Diego, California. Their telephone number is (619)450-9333. The part
number for the PCI interface chip is S5933.
* Ziatech, http://www.ziatech.com has the CompactPCI spec in Acrobat.
CompactPCI uses the PCI timing and pinout with a eurocard format and
connector.
...
(more about ISA at ISA, EISA, VME, and other plug-in cards schematic.html#isa
specific PCI chips:
See robot_links.html#PLD for more FPGA information.
Using FPGAs to simulate CPUs computer_architecture.html#FPGA
``The complete package includes comprehensive specification and design documentation, a comprehensive verification suite, and a test application.''
...
The PCI Bridge Soft Core supports common ASIC and FPGA libraries and is highly configurable including options for Master/Target or Target-only as well as for Host or Guest operation. You can download the PCI Bridge Soft Core from the OpenCores PCI Project Website at http://www.opencores.org/projects/pci .
PCI development tools:
/From pci-sig-request at znyx.com Tue Oct 17 15:12:26 1995
/Resent-From: pci-sig-request at znyx.com
/Resent-Date: Tue, 17 Oct 1995 11:13:08 -0700 (PDT)
/Date: Tue, 17 Oct 1995 11:13:08 -0700 (PDT)
/From: "John M. Keefe, Jr." <keefe at magma.COM>
/Subject: Re: useful tools (DEC PPB eval)
/To: PCI SIG <pci-sig at znyx.com>
/Mime-Version: 1.0
/Content-Type: TEXT/PLAIN; charset=US-ASCII
/Resent-Message-Id: <"Cfl2p3.0.iW2.7t-Wm"@dart>
/X-Mailing-List: <pci-sig at znyx.com> archive/latest/1421
/X-Loop: pci-sig at znyx.com
/Resent-Sender: pci-sig-request at znyx.com
/Content-Length: 1693
/X-Lines: 35
/Status: RO
> The part number on the board is 5023331-01. Another nice thing is that the
> DEC rep locally was able to lend us one until ours came in the mail. We
> encountered no compatability problems which were related to the hardware
> itself.
Of course it's compatible. The DEC PPB eval board is the one the PCI SIG
uses as its "bridge test board" during the compliance testing workshops.
I heartily concurr with the endorsement of this board. We couldn't have
completed the design of our PCI bus expansion box without two of these
critters in the hardware lab.
Another handy tool we've used extensively is a Catalyst Active Extender
(number PCI532-189) which allows "hot" card swapping, has probe pins for
every PCI connector pin and, because it is "active" doesn't add anything
to the bus loading (it's very nicely buffered with fast bus transceivers).
Catalyst is in San Jose at (408)268-4145
/john
------------------------------------------------------------
_/ _/ _/ _/_/_/ _/ _/ _/
_/_/ _/_/ _/ _/ _/ _/ _/_/ _/_/ _/ _/
_/ _/_/ _/ _/ _/ _/ _/ _/_/ _/ _/ _/
_/ _/ _/ _/_/_/_/ _/ _/_/_/ _/ _/ _/ _/_/_/_/
_/ _/ _/ _/ _/ _/ _/ _/ _/ _/
_/ _/ _/ _/ _/_/_/ _/ _/ _/ _/
------------------------------------------------------------
John M. Keefe, Jr. PCI Expansion Box Prod Mgr
Mesa Ridge Technologies -- MAGMA email: keefe at magma.com
6725 Mesa Ridge Road #100, Tel: (619) 457-0750
San Diego, CA 92121 Fax: (619) 457-0798
------------------------------------------------------------
From: tadejm at opencores.org Subject: Open Source PCI Bridge Soft Core Date: Sun, 24 Feb 2002 16:45:49 +0100 Hello, I thought this could be interesting to you. If you have a colleague interested in the subject, I'd like to ask you if you can forward this email to him/her. The OpenCores organization announces the immediate availability of the open-source, free, complete 33/66MHz 32-bit PCI Bridge Soft Core solution. PCI Bridge Complete & Tested The PCI Bridge Soft Core is a complete, synthesizable RTL (Verilog) code that provides bridging between the PCI and a WISHBONE (System-on-Chip) bus. The complete package includes comprehensive specification and design documentation, a comprehensive verification suite, and a test application. Test application is a "VGA card" implemented using a Xilinx Spartan II device on a PCI development board from Insight Electronics. PCI bridge core is connected to a simple VGA controller core forming a system-on-chip and comes with a Linux frame buffer device driver. The PCI Bridge Soft Core supports common ASIC and FPGA libraries and is highly configurable including options for Master/Target or Target-only as well as for Host or Guest operation. You can download the PCI Bridge Soft Core from the OpenCores PCI Project Website at http://www.opencores.org/projects/pci. OpenCores invites companies and universities to use our PCI Bridge Soft Core in your projects. Our main motivation and the sole reason for launching the PCI project has been and is to see the core used in many different projects. What we have in mind is a development much like that of open-source software (e.g. Linux). About OpenCores OpenCores is an organization whose main objective is to design, reuse, and integrate IP cores under the General Public License (GPL) helping the concept of freely available, open- source hardware to emerge and become visible and apparent. For more information about our projects and us, please visit us at http://www.opencores.org. We are also looking for organizations interested to support/sponsor OpenCores projects. Best regards, Tadej Markovic OpenCores PCI Team
(flagrantly copied from the handout from Dr. L. G. Johnson ) (see also Oklahoma State University System on Chip (SoC) Design Flows for use with Magic, Cadence, Synopsys, and MOSIS http://avatar.ecen.okstate.edu/projects/scells/ )
tesla.ceatlabs.okstate.edu provides all unix-based CAD tools.
tacoma.ceatlabs.okstate.edu provides electronic mail services.
Access them from these facilities:
See the CEAT staff in EN302 for more information about these (except for the CIS machines).
If you don't have a direct connection, on your local X terminal type
hostname xhost tesla.ceatlabs.okstate.edu telnet tesla.ceatlabs.okstate.edu hostname DISPLAY=your.address:0 export DISPLAY
includes both and , for
Companies that build straight digital logic ICs, analog ICs, and MEMs chips. This includes
For companies that design and manufacture FPGAs, see computer_architecture.html#FPGA
For companies that *use* chips in their designs (satellites, medical equipment, HDTV machine_vision.html#hdtv , etc), see link_farm.html#interesting_companies .
For companies that may make the silicon IC obsolete, see nanotech.html#company for companies doing genetic engineering, molecular digital logic, and quantum computing.
high_voltage.html lists a few more companies.
machine_vision.html lists companies that either (a) sell DSP chips fast enough to handle video data rates, or (b) sell CCD or CMOS image sensors. or both.
http://www.mdl.sandia.gov/Micromachine/movies.html
Sandia National Laboratories http://www.sandia.gov/ (operated by Sandia Corp., a Lockheed Martin Company) is redeveloping the Pentium® prococesor space and is doing a lot of MEMS microsensor research. "Programmable Diffraction Grating", "Chem-lab-on-a-chip".
http://www.nsplus.com/ns/981024/nspin.html mirror http://www.newscientist.com/ns/981024/nspin.html has a picture of "a spider mite on top of a 0.3 millimetre diameter gear wheel. " "the mites often try to pick up and move the gears" a movie at http://www.mdl.sandia.gov/Micromachine/movies.html which also shows Aphid on Micromirror and lots of other cool movies.
National Semiconductor http://www.national.com/design/ Intel www.intel.com (Portland, OR; Phoenix, AZ; Sacramento, CA; Santa Clara, CA; Seattle-Tacoma, WA) http://www.intel.com/intel/oppty/ Cadabra http://www.cadabratech.com ASIC synthesis LogicVision www.bist.com Synplicity http://www.synplicity.com/ (makes Synplify, a Verilog and VHDL synthesis tool for FPGAs and CPLDs) MicroSim http://www.microsim.com/ sells "DesignLab", does digital and analog design, mixed A/D simulation, FPGA synthesis, and printed circuit board layout. Micro Industries http://www.microindustries.com (Westerville, Ohio) makes PCI passive-backplane CPU boards and PC/104 CPU boards. Digital http://www.digital.com/careers/ Minc Inc. (sells $495 VHDL Easy ... to design PLD, CPLD, FPGA from Actel, Altera, AMD/Vantis, Lattice, and Xilinx) www.minc.com
Most of the design tools mentioned in vlsi.html assume thin rectangular slabs of silicon, not balls.
Z80 8-Bit CPU Formed on Glass Substrate -- A World First. First Step Toward Futuristic "Sheet Computers"Sharp press release 2002 http://z80.info/sharp/z80_glas.htm
CG (Continuous Grain) Silicon technology ... ... This technology allows digital logic, including LCD driver and power supplies, I/O interfaces, and signal processing circuitry, to be integrally formed on the same glass substrate as an LCD display. ... opens up the possibility of integrating on the same glass substrate not only functional peripheral components, particularly LCD display components and LCD driver ICs, but also a wide range of data processing circuit logic, including CPUs, memory, image compression/decompression circuitry, and the like. This new success based on CG-Silicon technology represents the first step on the road toward the development of futuristic ultra-thin "sheet computers" and "sheet TVs." ...
The Berkeley Intelligent RAM (IRAM) project http://iram.cs.berkeley.edu/ seeks to understand the entire spectrum of issues involved in designing general-purpose computer systems that integrate a processor and DRAM onto a single chip - from circuits, VLSI design and architectures to compilers and operating systems. IRAM should offer several advantages over today's solutions, including considerably reduced latency and dramatically increased bandwidth to main memory, reduced power and energy consumption, and reduced space and weight for embedded, portable, desktop, and parallel computer systems.
[FIXME: f-cpu mailing list eGroup home: http://www.eGroups.com/list/f-cpu ]
[FIXME: is there a Wikipedia article on computational RAM yet? http://en.wikipedia.org/wiki/Iram ]
[start message] Date: 1999-04-06 To: transhumantech-l at excelsior.org, f-cpu at egroups.com From: David Cary <d.cary at ieee.org> Subject: Computational RAM Cc: Bcc: X-Attachments: Looks like some predictions by Eugene Leitl and others are already coming true. "Computational RAM: Implementing Processors in Memory" article by Elliot, Stumm, Snelgrove, Cojocaru, Mckenzie in _IEEE Design & Test of Computers_ http://computer.org 1999-01 p.32-41 :
From a programming point of view, computational RAM seems very similar to the CAM-8 http://www.im.lcs.mit.edu/cam8.html . -- David Cary "mailto:d.cary@ieee.org" "icbmto:N36 08.830' W97 03.443'" http://www.rdrop.com/~cary/ Future Tech, Unknowns, machine vision ><> <*> O- [end message]Computational RAM is a processor-in-memory architecture that makes highly effective use of internal memory bandwidth by pitch-matching simple processing elements to memory columns. Computational RAM can function either as a conventional memory chip or as a SIMD (single-instruction-stream, multiple-data stream) computer. When used as a memory, computational RAM is competitive with conventional DRAM in terms of access time, packaging, and cost. As a SIMD computer, computational RAM can run suitable parallel applications thousands of times faster than a CPU. ...
Motivation
... exploit the chip's wide internal data paths ... exploit the energy efficiencies that result from better utilization of memory bandwidth and localization of computations on a millimeter scale ...... a host CPU can read and write to any memory location during an external memory cycle. ...
Memory Bandwidth
DRAM is organized with a very wide internal data path ... a 1Mx16 bit, 1K-cycle-refresh DRAM selects 16 Kbits with the 10 bit row address, and then one of 1 024 sixteen-bit words for output when the column address is available. ... the width of the internal data path is 1K ... times the width of the external data path. In systems with large amounts of memory, multiplexing banks of RAM onto a narrow bus limits bandwidth even further. ... cache improves the bandwidth [but] only by a factor of four, leaving a gap of three and a half orders of magnitude ...... A more mainstream architectural alternative to pitch-matching processing elements to groups of sense amplifiers is to put a single RISC or vector processor in a DRAM chip. This [allows] conventional programs to be compiled and run .... [and] access to a wider bus (...256 bits) for cache or vector register fills than it would have if implemented on a separate chip. Still ... the 16 Kbit wide data path at the sense amplifiers multiplexes down by a factor of 64 or more. ...
Power consumption
Power consumption is rapidly becoming a key measure of merit of computer architecture ... An internal DRAM bus is much more energy efficient (as well as faster) than an external bus because shorter wires must be driven. ... We can save a sizeable portion [perhaps 1/2, depending strongly on access pattern] of the power by not driving signals off chip. ...Computational RAM architecture
... We have implemented both designs in silicon ... 16 Mbit DRAM processes.The simpler of the two processing elements ... supports bit-serial computation and has left, right, and wired-AND bused communication. The ALU [is] an 8-to-1 multiplexer ... we can implement an entire processing element (including the off-chip read/write path) with as few as 88 transistors ... The control signals (derived from a 13 bit SIMD instruction) are routed straight through a row of processing elements.
... The processing elements and support circuitry add 18% to the area of an existing DRAM design. A single processing element occupies an area of approximately 360 bits of memory (including the sense amplifier and decoder overhead). ...
Effects of DRAM technology
DRAM technology is quite different from the technologies usually used for processors ... processors use four or five layers. The difficulty is not technical, but economic: if the processor needs five layers of metal, the extra metal layers are wasted over the DRAM array. In a competing architecture that segregates processing and memory, the dominant silicon area devoted to memory will cost less.The characteristics and operating conditions of DRAM transistors make them slower than transistors in an equivalent ASIC or digital logic process. ...
In any technology, a processing element has shorter lines and hence can cycle faster (and dissipate less power) than the DRAM array. This makes it practical to interpose two processor cycles in each memory cycle.
DRAM also relies heavily on redundancy to improve yield, which would otherwise be quite low due to high densities and large dies. Processors, on the other hand, are usually designed without redundancy ... since they occupy a small fraction of die area and therefore have limited effects on yield. ...
Benchmarks
... The computational RAM philosophy is that largely sequential applications belong on the host, and the massively parallel component belongs in the memory. ...3x3 convolution 16 M: C-RAM runtime: 17.6 ms; Sun Sparc runtime: 113 s; C-RAM speedup ratio: 6 404 ...
Incidentally, testing is another application for which computational RAM obtains a parallel speedup. The processing elements can be tested and then, themselves, perform the memory tests in less total time than it would take to test a similar-capacity memory. ...
Additional information about computational RAM is available at http://www.ee.ualberta.ca/~elliott/cram/ ...
Send comments and questions about this article to Duncan Elliot duncan.elliott@ualberta.ca
Date: Wed, 1 Apr 1998 05:17:14 -0500 (EST)
Comment: Hx: Transhuman Technlogies
Originator: transhumantech at excelsior.org
Reply-To: <transhumantech at excelsior.org>
Sender: transhumantech at excelsior.org
Version: Autolist v0.2 - Copyright 1995 Planet X Engineering
From: Eugene Leitl <eugene at liposome.genebee.msu.su>
To: Multiple recipients of list <transhumantech at excelsior.org>
Subject: beefing up a Beowulf ; smart memories almost here at last
http://www.techweb.com/wire/story/TWB19980327S0002
Memory Module
(03/27/98; 10:55 a.m. EST)
By Stephan Ohr, EE Times
Engineers reacted with approval to Texas
Instruments's technology demonstration at
WinHec of DIMM memory modules
featuring embedded digital-signal
processors (DSPs). Called Basava, the
individual modules can fit in a standard
168-pin memory-module slot on a Pentium
II-based motherboard or into the 144-pin
slot in a portable computer. The module
looks and behaves like a standard
synchronous DRAM (SDRAM) bank to the
processor and operating system, but can be
awakened on command to rapidly perform a
high-Mips DSP task. When the task is
completed, the Basava returns to its role as a
dumb memory module.
Developed as an exercise at TI's Tsukuba
Research and Development Center in Japan,
the module is designed to offload
DSP-specific tasks from a Pentium II host.
A tight coupling of the DSP with SDRAM
improves performance, said Raj Pawate,
senior member of the technical staff at
Tsukuba. The module offers performance
that's almost an order-of-magnitude
improvement over DSP cards that rely on
the PCI bus to communicate data and
instructions. And it makes little impact on
system memory when DSP tasks are not
being performed.
The module uses a TMS320C6X DSP in its
168-pin version, and a TMS320C54X in its
144-pin version. The DSP is expected to
pop awake on command or on a cue from
the operating system. Then its first task is to
partition the memory on the module for
DSP tasks. While the entire 64 megabytes,
for example, of a DIMM might be available
while a DSP sleeps, the module might set 16
MB aside for use by the awakened DSP and
leave 48 MB for the Pentium II. In all cases,
the partitioning is to be transparent so that a
Pentium II host processor can continue its
tasks without interruption.
Pawate said that the Basava module has
already received electrical certification as a
memory module from the Electronic
Industries Association of Japan (EIAJ).
Software certification and operating system
support is also being sought from other
standards-making bodies and from
Microsoft.
Basava will be particularly useful for audio
and video DSP tasks like DVD playback or
motion JPEG compression, said Pawate.
But engineers who had passed through TI's
booth at WinHec had imaginative ideas of
their own. "You need lots of bandwidth for
motion display," said Charles Marslett, a
consumer digital entertainment software
engineer with VLSI Technology, in Tempe,
Ariz. "But this would also help with system
debugging." Many large systems based on
gate arrays are difficult to simulate and test,
he volunteered.
Emulation tool vendors like Quickturn
Systems currently provide FPGA and
programmable-logic boards as targets for
gate-array development and simulation.
Basava could take their place, the engineer
said. "The DSP memory won't be as fast as
the Quickturn system," Marslett speculated,
"but it will be a lot smaller and cheaper."
See also:
http://www.techweb.com/wire/news/1997/10/1016ti.html
3 GFlops/$50 by y2k.
IBM ... has found a way to efficiently place both logic and memory circuits on a single piece of silicon. ...
"Until now, having processing power and data on separate chips was like having the materials you need to do your job in another office," said Bijan Davari, ... vice president of development for the IBM Microelectronics Division. "This forces you to keep going next door to get what you need. By placing logic and DRAM together on a single chip, we're making sure that the processor has what it needs close at hand, allowing it to operate more efficiently."
clever methods and ways of representing numbers, building addition, subtraction, multiplication, etc. out of bits and gates.
Building more complicated things out of bits and gates. Starting with 8 bit bytes, addition, subtraction, etc.
See also
Once you have multiplication and division on integers, see 1d_design.html for building more complicated things: floating point, trig functions, etc.
From: "Ralph Mason" <ralphmason at geocities.com>
Subject: Re: Parity calc for the PIC
Date: 25 Sep 1999 00:00:00 GMT
...
If you need to test for more than one bit set in a register.
if ( r & (r-1))
{
/* more than one bit is set in r */
}
Ralph
Lots of similar short, clever little subroutines are available at http://www.interstice.com/~sdattalo/technical/software/pic/picprty.html (also has links to Linux-based PIC simulators)
xp_new = bitmajority(xp, bitcomplement(xm), z) << 1; xm_new = bitxor(xp, xm, z).(When iterated with z=0, this eventually converges on xp = 0, xm = -x). To subtract any 2's complement value z from the accumulator in one cycle (without having to invert all the bits and add one and wait for this to propagate), (same as adding ~(z-1)),
xp_new = bitxor(xp, xm, z). xm_new = bitmajority(bitcomplement(xp), xm, z) << 1;(When iterated with z=0, this eventually converges on xp = x, xm = 0). (This is, in effect, negating the register by swapping xp with xm, then using the above addition algorithm, then swapping xp with xm again).
DAV first read about this (1999-04-11) in section 40 of the preliminary writeup http://sunburn.stanford.edu/~knuth/mmix.ps.gz (which has a proof) for the MMIX 2009 computer_architecture.html#mmix .
Virtual Socket Interface Alliance (VSIA) http://www.vsi.org/ is working on a open, standard, on-chip bus; already has some standard on-chip bus alternatives on their web page A standard on-chip bus would greatly simplify designing "system on a chip" reusing existing designs.
Programmable Arithmetic Devices for High Speed Digital Signal Processing http://infopad.eecs.berkeley.edu/spartan/talks_papers/dchen_phd/thesis_html/thesis.html includes "Limitations of FPGAs" and a nice chart of frequency v. what sorts of devices can handle those frequencies. also "Logic and VLSI Implementation" of the PADDI ("Programmable Arithmetic Devices for High Speed Digital Signal Processing") architecture.
Sand Microelectronics http://www.sandmicro.com/ claims to be "the leading provider of intellectual property (IP) with a focus on industry standard bus interfaces such as PCI, USB and 1394."
MEMS http://dolphin.eng.uc.edu/
Potential Nanoelectronic Two-State Devices http://www.mitre.org/research/nanotech/potential2state.html includes a review of Conventional Microelectronic Two-State Devices, the limits to scalability they have, "the 0.1 micron barrier." and proposed new devices that can be made even smaller.
IDaSS: ASIC lay-out of a 'Peripheral Control Cell' processor core ("can be considered an 8 bit RISC machine.") http://www.eb.ele.tue.nl/proj/idass8x3.html Nice picture !
http://www.us.design-reuse.com/ claims to be "The world's largest directory of Virtual Components, Software and Services for designing systems on chip".
icBIST 3.0 embedded test technology "is said to result in significant reductions in test development and manufacturing test costs" ... at-speed test ... support for mixed-signal cores ... (integrated circuit Built In Self Test) ... Logicvision Inc. http://www.logicvision.com/
OptoMOS relays http://www.cpclare.com
http://www.mrc.uidaho.edu/vlsi/ many links to VLSI information, including job opportunities, ...
Chip people http://www.engr.uky.edu/EE/Stroud/people.html (chip images; screen-captures from Magic)
CPU Info Center http://infopad.EECS.Berkeley.EDU/CIC/ (info on low-power CPU design)
Smithsonian institute interview with Seymour Cray http://innovate.si.edu/history/cray/cray33.htm Aesthetics, "the liquid that we're using to cool our Cray 2's, Cray 3's, Cray 4's, is also used as artificial blood in human beings", a bit of nanotech, "focused on the thing" vs. "people person", the necessity of taking risks,
Physics of Computation (Physcmp), Carver Mead's group http://www.pcmp.caltech.edu/ lots of chip design pointers. [perhaps suggest irsim -- or ask if 'log' is superior in every way]
Computer Architecture newsgroups http://x1.dejanews.com/bg.xp?level=comp.arch
Berkeley Design Technology, Inc. http://www.bdti.com/ sells the "Buyer's Guide to DSP Processors" for a mere $ 2 450.
[vlsi] http://www.letu.edu/student/orgs/acm/minutes/Future.htm current and future chip technology [vlsi#mems] http://www.ee.surrey.ac.uk/Personal/D.Banks/usys_i.html MICROSYSTEMS, MICROSENSORS & MICROACTUATORS: An Introduction. Danny Banks. <D.Banks at surrey.ac.uk>
Exponential Technology http://www.exp.com/products/x704/bicmos.html "bipolar logic was widely acknowledged to be faster than CMOS, but most people believed it was impossible to use bipolar logic for a mainstream microprocessor because it required too much power and cost too much to manufacture. ... the X704TM, a PowerPCTM compatible microprocessor. ... With this new BiCMOS technology, the X704 utilizes both bipolar and CMOS technologies without compromising the bipolar transistors. As a result, the bipolar transistors are small enough and fast enough to be used for complex logic. ... "
VLSI TUTORIALS http://et.nmsu.edu/ETCLASSES/vlsi/AUTHOR.HTM by Sonia Champion Jeffrey Edaakie New Mexico State University http://et.nmsu.edu/ETCLASSES/vlsi/files/VLSI.HTM
[MEMS] http://imems.mcnc.org/imems/imems.html "the surface micromachining process integrated with BiCMOS electronics used by Analog Devices for its commercial accelerometers is available through MCNC for experimental project chip use by the general U.S. public"
http://www.cybercom.net/~ahvezda/ gEDA - GPL'd Electronic Design Automation tools, some FORTH info, lots of info on designing and building (!) (homebrew wire-wrapping, making PCB boards, programming PLDs, GALs, ROMS, FPGAs, and minimal 68K systems) your own CPU, bootstrapping a new system, and some Theory/Speculation on future computers. computer_architecture.html#forth
What is "Delay Calculation Language (DCL) IEEE 1481" ?
VLSI Microprocessors: A Guide to High-Performance Microprocessor Resources http://www.microprocessor.sscc.ru/
The Institute for Interconnecting and Packaging Electronic Circuits (IPC) http://www.ipc.org/
David Harris
http://www.stanford.edu/~harrisd/
invented "Opportunistic
Time-Borrowing Domino circuits"
http://patent.womplex.ibm.com/cgi-bin/viewpat.cmd/5517136
while working for Intel.
Teaches High Speed CMOS Circuit Design (VLSI) at MIT
wrote (shareware) RoboWar for the Macintosh
has
Skew-Tolerant Circuit Design (thesis draft)
online.
the Scalable Coherent Interface (SCI) Users, Developers, and Manufacturers Association http://www.scizzl.com/ (ANSI/IEEE Std 1596)
The Scalable Coherent Interface (Local Area MultiProcessor) is effectively a combination computer backplane bus, processor memory bus, I/O bus, high performance switch, packet switch, ring, mesh, local area network, optical network, parallel bus, serial bus, information sharing and information communication system that provides distributed directory based cache coherency for a global shared memory model and uses electrical or fiber optic point-to-point unidirectional cables of various widths. Typical performance is currently in the range of 200 MByte/s/processor (CMOS) to 1000 MByte/s/processor (BiCMOS) over distances of tens of meters for electrical cables and kilometers for serial fibers. SCI/LAMP was designed to be interfaceable to common buses such as PCI, VME, Futurebus, Fastbus, etc., and to I/O connections such as ATM or FibreChannel. It was designed to work in complex multivendor systems that grow incrementally, a harder problem than interconnecting processors inside a single product (e.g. MPP). Its cache coherence scheme is comprehensive and robust, independent of the interconnect type or configuration, and can be handled entirely in hardware, providing distributed shared memory with transparent caching that improves performance by hiding the cost of remote data access, and eliminates the need for costly software cache management.
Viewlogic Systems, Inc. http://www.viewlogic.com/ "full suite of Design Entry, Enterprise, Simulation, FPGA and High Speed analysis products." electronic design software
Cavendish Laboratory Microelectronics Research Centre http://www.qdo.com/Exp/MRC1/
_HDI: The magazine for High-Density Interconnect_ http://www.hdi-online.com/ Free Subscription to the paper version http://www.hdi-online.com/forms/freesub.htm
Flip Chip Technologies, LLC http://www.flipchip.com/ has a Design Guide http://www.flipchip.com/flipsec7/desn.htm to help you design flip chip ICs compatible with their process.
[vlsi ? FreeCAD ?] ProperCAD Research Group Home Page http://www.crhc.uiuc.edu/ProperCAD/ "The ProperCAD project at the University of Illinois's Center for Reliable and High-Performance Computing is an investigation of the use of parallel computing resources for the most compute intensive VLSI CAD algorithms."
the laboratory of Professor Christof Koch http://www.klab.caltech.edu/ "Biophysics of Computation in Single Neurons", "Neuromorphic Analog VLSI Vision Systems", pretty visual illusions. http://www.illusionworks.com/
_Integrated System Design_ magazine http://www.netline.com/isd/
Topics covered in Integrated System Design include:
FPGA floor planning, clock and power distribution, low-power design, hardware-software codesign, ASIC prototyping, state machine design, design reuse, embedded system design, library development
Each issue contains a practical system, design story relating to such topics as:
set-top boxes, PDAs, graphics chips, medical electronics, networking systems, wireless communications
http://www.ece.ucdavis.edu/sscrl/ "The SSCRL Lab is located in 2201 Engineering Unit II on the UCDavis Campus. The lab is dedicated to designing, building and testing Integrated Circuits (ICs)." SSCRL maintains the comp.lsi.cad FAQ http://www.ece.ucdavis.edu/sscrl/clcfaq/faq/
Synopsys, Inc. http://www.synopsys.com/
Analog Devices, Inc. http://www.analog.com/ "develops, manufactures and markets high-performance analog, digital, and mixed-signal integrated circuits (ICs) used in signal-processing applications." Has a nice online part search; lots of app notes online. Was the first company (I think) to commercially sell umachined MEMs devices -- their accelerometers.
Open-24-7.com http://www.open-24-7.com/ sells GaAs (gallium arsenide) and Si (silicon) wafers.
CSEM http://csem.ch/ sells MEMS accelerometers.
"CPLD design methods are moving to open languages like VHDL, Verilog, and Jam" "The Jam language is a freely licensed and open standard. Most of the source code required for the Jam Player is contained in the Jam Device Programming and Test Language Developer's Kit available at http://www.altera.com/ " also see http://www.jamisp.com/
_Solid State Technology: The International Magazine for Semiconductor Manufacturing_ http://www.solid-state.com/ (gives free subscriptions to qualified individuals)
Project: Von Neumann http://www.krl.caltech.edu/~charles/alife-game/ a freeware computer game, played with human and AI "probes" that learn.
ECE 474/574 http://www.ece.orst.edu/~ece474/ includes links to many sites with VHDL information, and some documentation on synthesis.
Open Verilog International http://www.ovi.org/
http://www.cadence.com/main.html
Advanced Micro Devices, Inc. http://www.amd.com/
"Enable Semiconductor has spun off its existing low-power IC business into a new privately held corporation, NanoAmp Solutions." -- http://www.techweb.com/wire/story/TWB19990304S0010
Switching from aluminum to copper was a big deal ( http://www.research.ibm.com/resources/magazine/1997/issue_4/copper497.html ). Why don't semiconductor manufacturers just use gold ?
comp.lang.vhdl http://www.dejanews.com/[ST_rn=bg]/dnquery.xp?query=~g%20comp.lang.vhdl
comp.lang.verilog http://www.dejanews.com/[ST_rn=bg]/dnquery.xp?query=~g%20comp.lang.verilog
http://www.sandcraft.com/ | http://wpi.supersites.net/ncworldjobbankn2/sandcraft/home.htm | http://supersite.net/techjobsh2/sandcraft/home.htm VLSI jobs ???
The Center for Space Microelectronics Technology (CSMT) http://csmt.jpl.nasa.gov/csmtpages/index.html "The Center concentrates on innovative high-risk, high-payoff concepts and devices ... sensors for [the entire] the electromagnetic spectrum ... microinstruments and microelectronic systems for miniature spacecraft, and high-performance computing both in space and on the ground"
Ultrathin Packaging of Multiple Integrated-Circuit Chips http://www.nasatech.com/TSP/PDFTSP/LEW16545.pdf "total package thickness ... less than 5 thousandths of an inch (5 mils) thick. By comparison, a piece of copy machine paper is roughly 4 mills thick."
http://bob.eecs.berkeley.edu/~burd/software/maker2html/ex10/LagerBook.html Anatomy of a Silicon Compiler tools for interactive floorplanning and routing very large VLSI designs a tool that translates a algorithm in (almost) C to microcode to target any supplied datapath description. Introduction to VLSI Systems http://www-leland.stanford.edu/class/ee271/ (class information) Design Projects in VLSI Systems http://www-leland.stanford.edu/class/ee272/ class information, and links to some interesting projects. Magic home page http://www.research.digital.com/wrl/projects/magic/ information on getting the manuals and latest source code to Magic; technology files, etc. ELE537 VLSI Systems Design Homepage http://www.ele.uri.edu/Courses/ele537/ LEVO logic (a fault-redundant massively parallel processor that re-orders instructions in a sequential stream to feed into 32 processing elements; detects dependency constraints on-the-fly ... speedups of perhaps 20x (theoretically) over sequential execution ... if one PE fails, it is skipped over -- fault tolerant) broken links to cell libraries daly at ele.uri.edu
Subject: Re: Beginner in need of help Date: 1999/07/16 Author: Steven K. Knapp <sknapp at optimagic.com> Posting History The Programmable Logic Jump Station at http://www.optimagic.com may be a good place to start. It has links to most information on FPGAs, CPLDs, and associated software. You can also find links to books and tutorials. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp at optimagic.com Web: http://www.optimagic.com -----------------------------------------------------------http://www.optimagic.com
To: freehdl at smash.gatech.edu, geda-dev at geda.seul.org, linux-eda at dv.org Subject: gEDA: Savant version 1.01 available From: dmartin at clifton-labs.com (Dale E. Martin) Date: 16 Jun 1999 17:16:00 -0400 Lines: 27 Sender: owner-geda-dev at geda.seul.org Reply-To: geda-dev at geda.seul.org X-To-Get-Off-This-List: mail majordomo at geda.seul.org, body unsubscribe geda-dev I'm please to announce the release of Savant version 1.01. Savant is the University of Cincinnati's VHDL Analyzer/code generator, released under the LGPL. This version contains bug fixes for various problems discovered by users of version 1.0. Version 1.01 is currently available in source, as Debian binary packages (potato or slink), and RedHat 6.0 binary packages. Solaris sparc packages could be generated if there is any interest - let us know. All files are available from "ftp://ftp.ececs.uc.edu:/pub/users/dmartin". Also, there is now a savant-users mailing list available. See info about subscribing to it at "http://www.ececs.uc.edu/~paw/savant/". Additionally, paid commercial support is being offered by Clifton Labs, Inc. Send email to "savant at clifton-labs.com" for info. As always, we thank you for your feedback and welcome any comments at all that you have about Savant. -- +---------------------- pgp key available -----------------------+ | Dale E. Martin | Clifton Labs, Inc. | Senior Computer Engineer | | dmartin at clifton-labs.com | http://www.clifton-labs.com | +----------------------------------------------------------------+
From: Pasquale Corsonello <pascor at deis.unical.it> Subject: Announcement: New high-speed low-power adders Date: 23 Jul 2000 00:00:00 GMT Message-ID: <397B10C8.76980EE9@deis.unical.it> Content-Transfer-Encoding: 7bit To: vkantabu at computer.org X-Accept-Language: en Content-Type: text/plain; charset=us-ascii X-Complaints-To: news at cineca.it X-Trace: news.cineca.it 964366497 12552 160.97.25.141 (23 Jul 2000 15:34:57 GMT) Organization: DEIS-University of Calabria Mime-Version: 1.0 NNTP-Posting-Date: 23 Jul 2000 15:34:57 GMT Newsgroups: comp.arch,comp.arch.arithmetic,comp.arch.dsp,comp.arch.fpga,comp.lsi *******To anyone is involved in VLSI digital designs******* This is to announce a new family of adders that involve a new bit block structure that computes propagate signals called "carry strength" in a ripple fashion. A 32-bit carry-skip adder designed using the new method and realized using 0.6um CMOS technology shows a performance gain of more than 30% with respect to a conventional carry-skip adder, and reaches a performance comparable with that of a traditional block-CLA saving more than 26% silicon area and more than 34% power. Results will be discussed at the SSGRR 2000 Conference in L'Aquila, Italy (http://www.ssgrr.it/en/conferenza/index.htm). The new approach has been also applied to spanning-tree adders (Lynch-Swartzlander 1991 and Kantabutra 1993). Results will be broadcast at the First Online Symposium for Electronics Engineers (www.techonline/OSEE) Please, anyone interested in these results may visit our Web sites or contact us. http://www.ing.unirc.it/didattica/elettr01/index.html http://www.isu.edu/~kantviti/ ********************************************** *Pasquale Corsonello Microelectronic and Microsystem *Laboratory *Department of Electronic Computer Science and System *University of Calabria *Loc. Arcavacata di Rende - RENDE (CS) - 87036-ITALY *Tel:+39 984 494708 Fax:+39 984 494713 *email: pascor at deis.unical.it * http://www.ing.unirc.it/didattica/elettr01/index.html ********************************************** Vitit Kantabutra, Ph.D. Associate Professor of Computer Science College of Engineering Idaho State University Pocatello, Idaho 83209-8060 U.S.A.
Don't miss the Chip Gallery http://pasta.stanford.edu/hssp/chip.htm (Thanks for the link, Jecel Assumpcao Jr. !) [low power]
To: geda-dev at seul.org, mcmahill at mtl.mit.edu Subject: Re: gEDA: vhdl simulator X-Mailer: Mew version 1.94.1 on Emacs 20.7 / Mule 4.0 (HANANOEN) Date: Sun, 26 Nov 2000 16:22:48 +0100 From: Magnus Danielson <cfmd at swipnet.se> X-Dispatcher: imput version 991025(IM133) Lines: 49 Sender: owner-geda-dev at seul.org Reply-To: geda-dev at seul.org X-To-Get-Off-This-List: mail majordomo at seul.org, body unsubscribe geda-dev From: mcmahill at mtl.mit.edu Subject: gEDA: vhdl simulator Date: Sun, 26 Nov 2000 04:10:15 -0500 (EST) > > > can anyone recommend a freely available VHDL simulator? Someone has been > asking me and he needs VHDL (for school) rather than verilog. Well, I know of three VHDL simulators: 1) Electric Released under GPL and is found from FSF (http://www.fsf.org). It's a graphical environment type of tool, it can also do synthesis. It has limited VHDL simulation support (structual VHDL) but may be usefull. I haven't checked the latest versions thought. 2) Savant Released under GPL or LGPL, I don't recall. It is trying to grasp the full VHDL, but you are "blind" in that there is simply no such thing as waveform dumping. I have as a longterm goal to contribute on that so that it can be usefull. However, things like being able to handle IEEE libs got in the way and has delayed much of the waveform dumping work. However, I've learned some on the internal stuff so maybe, maybe. 3) FreeHDL Released under GPL (http://www.freehdl.seul.org/) I haven't seen much movement in this. It seems like an atempt to be an Savant (which used to not be really that free) but looking more on practical things like waveform dumping. It got somewhere but then I didn't see any movements. I'd love to see that they make progress. Please look at http://www.opencollector.org/summary.php3 to find some more leads. The only possibly interesting thing that I find there is the PICA. Now, if you are looking for something like ModelSim, the free tools are not really there yeat. IMHO is Savant the framework which migth be best to work on (which is why I try to do that, when I have time) in order to acheive real VHDL simulation capabilities for free. We don't have the graphical frontend in Savant, the main work really lies in the way the hole simulation and VHDL compliance stuff work. Savant also suffers from a number of defiencies IMHO, but eventually some of that may be washed out. Cheers, Magnus
To: geda-dev at seul.org
Subject: Re: gEDA: vhdl simulator
User-Agent: Mutt/1.2.5i
From: Dale E Martin <dmartin at clifton-labs.com>
Date: Tue, 28 Nov 2000 09:10:42 -0500
Sender: owner-geda-dev at seul.org
Reply-To: geda-dev at seul.org
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> can anyone recommend a freely available VHDL simulator? Someone has been
> asking me and he needs VHDL (for school) rather than verilog.
Hi! I'm one of the primary developers for the SAVANT project. SAVANT is
an LGPL VHDL '93 system. It includes an analyzer, c++ code generator, and
an extensible intermediate form. If you'd like more information, email me
and/or check out the web pages at:
http://www.ececs.uc.edu/~paw/savant
Thanks,
Dale
--
+---------------------- pgp key available -----------------------+
| Dale E. Martin | Clifton Labs, Inc. | Senior Computer Engineer |
| dmartin at clifton-labs.com | http://www.clifton-labs.com |
+----------------------------------------------------------------+
Date: Tue, 28 Nov 2000 03:35:08 -0800 (PST) From: Michael Laajanen Subject: Re: gEDA: vhdl simulator To: geda-dev at seul.org Sender: owner-geda-dev at seul.org Reply-To: geda-dev at seul.org X-To-Get-Off-This-List: mail majordomo at seul.org, body unsubscribe geda-dev HI, I meet a guy a few years ago and HIS company was develping a free VHDL/Verilig simulator for school use running under Unix and PC using tcl/tk. His name is Kameron Wong and his company is at www.bluepc.com /michael --- mcmahill at mtl.mit.edu wrote: > > > can anyone recommend a freely available VHDL simulator? Someone has > been > asking me and he needs VHDL (for school) rather than verilog. > > Thanks > -Dan > > ===== michael_laajanen at yahoo.com Create like a God, command like a King, work like a Slave
Date: Thu, 30 Nov 2000 00:03:43 +1100 From: Hamish Moffatt To: geda-dev at geda.seul.org Subject: Re: gEDA: vhdl simulator Mail-Followup-To: geda-dev at geda.seul.org User-Agent: Mutt/1.0.1i Sender: owner-geda-dev at seul.org Reply-To: geda-dev at seul.org X-To-Get-Off-This-List: mail majordomo at seul.org, body unsubscribe geda-dev On Sun, Nov 26, 2000 at 04:10:15AM -0500, mcmahill at mtl.mit.edu wrote: > can anyone recommend a freely available VHDL simulator? Someone has been > asking me and he needs VHDL (for school) rather than verilog. Here's a solution which is free in monetary terms but not intellectual terms; VHDLSimili from www.symphonyeda.com .. it runs test benches and can apparently output waveform dumps, but is command line driven and doesn't have a fancy GUI etc. I haven't used it but I have heard good reports. Hamish -- Hamish Moffatt VK3SBwww.symphonyeda.com
``Aldec Inc., a longtime provider of FPGA design tools, will make its first foray into the ASIC market this week with Riviera, a Linux-based mixed-language simulator. Riviera simulates VHDL, Verilog and EDIF and comes with an HDL editor and source-level debugger.
...
Some of Aldec's FPGA customers are looking for more capacity and setting up server farms, Rinehart said, and Linux offers those users better performance than Windows NT. Aldec has found that Riviera runs up to five times faster in batch mode under Linux than under Windows NT on the same hardware platform, he said.
...
Riviera starts at $12,495, including the HDL editor and debugger. It runs on Red Hat Linux.
``NanoBlock circuits'' ``The FSA process uses single crystal silicon NanoBlock^(TM) ICs fabricated on standard silicon wafers, in industry standard CMOS wafer foundries. Standard 6-inch CMOS wafers can yield millions of tiny (tens of microns square) NanoBlock(TM) ICs.'' ``Alien Technology ... has prototype chips that are smaller than the ``D'' marking on a dime that indicates the coin was fabricated at the Denver mint'' ``the per-chip price should drop to 5 cents apiece [before 2007]. He hopes to see them plummet to a penny or less by 2011.''``Alien Technology has developed, and holds exclusive patent rights to, a manufacturing assembly technology called Fluidic Self Assembly (FSA) that allows for the efficient placement of arbitrarily large numbers of small components across a surface in a single operation. The company plans to first use the technology to distribute pixel drive circuits to make electronic displays, but it will also be applied to other problems, such as antennas, sensors and very low-cost RFID tags.''
-- http://buffy.eecs.berkeley.edu/IRO/Summary/01abstracts/chapter9.html also see http://www-video.eecs.berkeley.edu/~vdai/ [FIXME: also related to data_compression # lossless image compression] []...
...massively parallel arrays of writing instruments...
A state-of-the-art pattern generator, which can write 4X mask plates at the rate of one plate per hour, could in principle be speeded up to write directly onto wafers. However, today’s optical lithography projection systems maintain a throughput of one wafer per minute. ... Also, ... the image on a plate only covers about 1/100 of the wafer area. Thus the challenge of data handling for maskless lithography is to accomplish a 10,000-fold throughout improvement over today's state-of-the-art mask writers.
... assume a wafer 300 millimeters in diameter and a writing pixel size of 25 nanometers. For the wafer to be written in 60 seconds, data rates of 1.9 tera-pixels per second are needed. These tera-pixel writing rates and terabit storage forces the adoption of a massively parallel writing strategy and system architecture.
...
... we estimate that a compression ratio of 25 is necessary to achieve the data rates desired. ... lossless layout compression for maskless lithography. The results of our compression experiments ... JBIG, a compression standard developed for bi-level images, performs well for non-dense layout. However for dense, regularly arrayed memory cells, its performance is hampered by the limited ten-pixel context, which is not sufficient to model the repetition of large thousand-pixel cells. On the other hand, ZIP, based on LZ77, takes full advantage of repetitions to compress memory cells, but performs poorly in non-regular layout. Our 2D-LZ improves on the basic LZ77 technique, by extending matching to two dimensions. Several refinements of the basic 2D-LZ technique are implemented to improve compression performance. For all the different layouts tested, at least one of the three compression schemes is able to achieve a compression ratio of at least 20. ...
...
... By placing the edge of one chip directly in contact with its neighbor, it may be possible to move data 60 to 100 times as fast as the present top speeds.
...
"It could represent the end of the printed circuit board," said Jim Mitchell, director of Sun Laboratories ...
...
... Dr. Sutherland, Robert J. Drost and Robert D. Hopkins ... were able to send data at a speed of 21.6 billion bits a second between chips in a scaled-down version of the new technology. By comparison, an Intel Pentium 4 processor, the fastest desktop chip, can transmit about 50 billion bits a second. But .. researchers ... expect to reach speeds in excess of a trillion bits a second, which would be about 100 times the limits of today's technology.
Currently, computer data is moved in and out of an integrated circuit through ... special pads that ring the edge of each chip. While the pads are small, they are vastly larger than the transistors and wires that make up the chip's circuitry.
A typical ... pad that is 100 microns wide, about the width of a human hair. Compared with the internal circuitry, this passageway requires relatively large amounts of power. Also, the size of the pads and wires necessarily limits the number there are to ferry information in and out of the circuit.
The new Sun chip has tiny transmitters that are only a few microns in width. In addition to having many more connecting points, the chip should consume far less power. ...
Chip-to-chip bottlenecks have long been a vexing challenge for computer designers, who have explored many ways of increasing the overall speed of systems that are composed of hundreds of chips.
Other potential technologies have included optical lasers and even the idea of quantum entanglement of electrons, which holds out the possibility of moving huge amounts of data instantaneously.
... the Sun design, employs an effect known as "capacitive coupling" to send electrical pulses at high speed. ...
...
The Sun technique could pack hundreds of chips in face-to-face checkerboard fashion far more densely than is possible today. The technique holds out the hope of attaining what had been one of Silicon Valley's far-off dreams: a computer packaging technique known as wafer-scale integration.
...
For decades, computer designers have tried to figure out how to make computer systems out of single large wafers. But designers have stumbled over the fact that it is virtually impossible to create large wafers that are free of defects.
Now the Sun researchers may have surmounted the hurdle with a simple mechanical solution -- having a bunch of small chips work together with the computing properties of a single wafer.
...
Mills is mentioned in the article "Analog Computation" by Leigh Hedger http://www.indiana.edu/~rcapub/v21n2/p24.html
...
Technically, today's chips are already slightly blurry at the edges. High-end chip designs compensate for this by putting less-critical circuitry in the corners. ...
...
A chip that's been cut loose from its wafer is called a die, and several die together are also called die, not dice. There's no particularly good reason for this grammatical inconsistency.
...
-- http://staticfreesoft.com/electric.html ... has some interesting GPL tools ...The ElectricTM VLSI Design System is a complete Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:
- Custom IC layout
- Schematic Capture (digital and analog)
- Textual Languages such as VHDL and Verilog
- Programmable logic (FPGAs)
Send comments, suggestions, bug reports to