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|
v 20050820 1
T 400 2900 9 10 1 0 0 0 1
Out2
T 400 2100 9 10 1 0 0 0 1
In2
T 400 1300 9 10 1 0 0 0 1
EnableB
T 400 500 9 10 1 0 0 0 1
SenseB
T 400 1700 9 10 1 0 0 0 1
Vss
T 400 900 9 10 1 0 0 0 1
Out3
T 2200 1100 9 10 1 0 0 6 1
In4
T 2200 700 9 10 1 0 0 6 1
Out4
P 300 2900 0 2900 1 0 1
{
T 100 2950 5 8 1 1 0 0 1
pinnumber=3
T 100 2950 5 8 0 0 0 0 1
pinseq=19
}
P 300 2500 0 2500 1 0 1
{
T 100 2550 5 8 1 1 0 0 1
pinnumber=5
T 100 2550 5 8 0 0 0 0 1
pinseq=2
}
P 300 2100 0 2100 1 0 1
{
T 100 2150 5 8 1 1 0 0 1
pinnumber=7
T 100 2150 5 8 0 0 0 0 1
pinseq=3
}
P 300 1700 0 1700 1 0 1
{
T 100 1750 5 8 1 1 0 0 1
pinnumber=9
T 100 1750 5 8 0 0 0 0 1
pinseq=4
}
P 300 1300 0 1300 1 0 1
{
T 100 1350 5 8 1 1 0 0 1
pinnumber=11
T 100 1350 5 8 0 0 0 0 1
pinseq=5
}
P 300 900 0 900 1 0 1
{
T 100 950 5 8 1 1 0 0 1
pinnumber=13
T 100 950 5 8 0 0 0 0 1
pinseq=9
}
P 300 500 0 500 1 0 1
{
T 100 550 5 8 1 1 0 0 1
pinnumber=15
T 100 550 5 8 0 0 0 0 1
pinseq=7
}
P 2600 700 2300 700 1 0 0
{
T 2400 750 5 8 1 1 0 0 1
pinnumber=14
T 2400 750 5 8 0 0 0 0 1
pinseq=8
}
P 2600 1100 2300 1100 1 0 0
{
T 2400 1150 5 8 1 1 0 0 1
pinnumber=12
T 2400 1150 5 8 0 0 0 0 1
pinseq=18
}
P 2600 1500 2300 1500 1 0 0
{
T 2400 1550 5 8 1 1 0 0 1
pinnumber=10
T 2400 1550 5 8 0 0 0 0 1
pinseq=13
}
B 300 300 2000 3300 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 2900 2700 5 10 0 0 0 0 1
device=SN754410
T 400 2500 9 10 1 0 0 0 1
In1
T 300 3650 9 10 1 0 0 0 1
L298N
T 2300 3700 8 10 1 1 0 6 1
refdes=U?
P 300 3300 0 3300 1 0 1
{
T 100 3350 5 8 1 1 0 0 1
pinnumber=1
T 100 3350 5 8 0 0 0 0 1
pinseq=6
}
T 400 3300 9 10 1 0 0 0 1
SenseA
P 2600 1900 2300 1900 1 0 0
{
T 2400 1950 5 8 1 1 0 0 1
pinnumber=8
T 2400 1950 5 8 0 0 0 0 1
pinseq=12
}
P 2600 2300 2300 2300 1 0 0
{
T 2400 2350 5 8 1 1 0 0 1
pinnumber=6
T 2400 2350 5 8 0 0 0 0 1
pinseq=17
}
P 2600 2700 2300 2700 1 0 0
{
T 2400 2750 5 8 1 1 0 0 1
pinnumber=4
T 2400 2750 5 8 0 0 0 0 1
pinseq=16
}
P 2600 3100 2300 3100 1 0 0
{
T 2400 3150 5 8 1 1 0 0 1
pinnumber=2
T 2400 3150 5 8 0 0 0 0 1
pinseq=15
}
T 2200 1500 9 10 1 0 0 6 1
In3
T 2200 1900 9 10 1 0 0 6 1
Gnd
T 2200 2300 9 10 1 0 0 6 1
EnableA
T 2200 2700 9 10 1 0 0 6 1
Vs
T 2200 3100 9 10 1 0 0 6 1
Out1
|
