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To: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
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Cc: Bitcoin Protocol Discussion <bitcoin-dev@lists.linuxfoundation.org>
Subject: Re: [bitcoin-dev] Libre/Open blockchain / cryptographic ASICs
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Good morning Luke,
Another thing we can do with scan mode would be something like the below ma=
sking:
input CLK, RESET_N;
input TESTMODE;
input SCANOUT_INTERNAL;
output SCANOUT_PAD;
reg gating;
wire n_gating =3D gating && TESTMODE;
always_ff @(posedge CLK, negedge RESET_N) begin
if (!RESET_N) gating <=3D 1'b1; /*RESET-HIGH*/
else gating <=3D n_gating; end
assign SCANOUT_PAD =3D SCANOUT_INTERNAL && gating;
The `gating` means that after reset, if we are not in test mode, `gating` b=
ecomes 0 permanently and prevents any scan data from being extracted.
Assuming scan is not used in normal operation (it should not) then inadvert=
ent ESD noise on the `gating` flip-flop would not have an effect.
Output being combinational should be fine as the output is "just" an AND ga=
te, as long as `gating` does not transition from 0->1 (impossible in normal=
operation, only at reset condition) then glitching is impossible, and when=
scan is running then `TESTMODE` should not be exited which means `gating` =
should remain high as well, thus output is still glitch-free.
Since the flip-flop resets to 1, and in some technologies I have seen a res=
et-to-0 FF is slightly smaller than a reset-to-1 FF, it might do good to in=
vert the sense of `gating` instead, and use a NOR gate at the output (which=
might also be smaller than an AND gate, look it up in the technology you a=
re targeting).
On the other hand the above is a tiny circuit already and it is unlikely yo=
u need more than one of it (well for large enough ICs you might want more t=
han one scan chain but still, even the largest ICs we handled never had mor=
e than 8 scan chains, usually just 4 to 6) so overoptimizing this is not ne=
cessary.
Regards,
ZmnSCPxj
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