From: Eugene Leitl (Eugene.Leitl@lrz.uni-muenchen.de)
Date: Thu Jan 23 1997 - 14:38:22 MST
(Well, it's outdated, but the basic arithmetics is still sound. Besides,
even naphthaline content can tell us something).
"Computer Architecture, a Quantitative Approach", John L. Hennessy &
David A. Patterson, Morgan Kaufmann Publishers, (1990), pp. 54-61.
Cost of an Integrated Circuit
Why would a computer architecture book have a section on integrated
circuit costs? In an increasingly competitive computer marketplace where
standard parts -- disks, DRAMs, and so on -- are becoming a significant
portion of any system's cost, integrated circuit costs are becoming a
greater portion of the cost that varies between machines, especially in
the high volume, cost-sensitive portion of the market. Thus computer
designers must understand the costs of the chips to understand the costs
of current computers. We follow here the American accounting approach to
the costs of the chips.
While the costs of integrated circuits have dropped exponentially, the
basic procedure of silicon manufacture is unchanged: A _wafer_ is still
tested and chopped into _dies_ that are packaged [...]. Thus the
cost of a packaged integrated circuit is:
Cost of die+Cost of testing die+Cost of pkgng.
Cost of integrated circuit = ----------------------------------------------
Final test yield
Cost of Dies
To learn how to predict the number of good chips per wafer
requires first learning how many dies fit on a wafer and then how to
predict the percentage of those that will work. From there it is simple to
predict cost:
Cost of wafer
Cost of die = ----------------------------------------
Dies per wafer * Die yield
The most interesting feature of this first term of the chip
cost equation is its sensitivity to die size, shown below.
The number of dies per wafer is basically the area of the wafer
divided by the area of the die. It can be more accurately estimated by
\pi * (Wafer diameter/2)^2 \pi * wafer diamtr. Test
Dies per wafer = -------------------------- - ------------------- - dies per
Die area \sqrt{2 * Die area} wafer
The first term is the ratio of wafer area (\pi r^2) to die area. The
second compensates for the "square peg in a round hole" problem --
rectangular dies near the periphery of round wafers. Dividing the
circumference (\pi d) by the diagonal of a square die is approximately
the number of dice along the edge. The last term is for test dies that
must be strategically placed to control manufacturing. For example, a
15-cm (ca. 6-inch) diameter wafer with 5 test dies produces 3.14 * 225/4
- 3.14*15/\sqrt{2} - 5 or 138 1-cm-square dies. Doubling the area -- the
parameter that a computer designer controls -- would cut dies per wafer
to 59.
But this only give the maximum number of dies per wafer, and the critical
question is what is the fraction of percentage of good dies on a wafer
number, or the _die yield_. A simple model of integrated circuit yield
assumes defects are randomly distributed over the wafer:
Defects per unit area * Die area
Die yield = Wafer yield * ( 1 + -------------------------------- ) ^ - \alpha
\alpha
where _wafer yield_ accounts for wafers that are completely bad and so
need not be tested and \alpha is a parameter that corresponds roughly to
the number of masking levels critical to die yield. \alpha depends upon
the manufacturing process. Generally \alpha = 2.0 for simple MOS
processes and higher values for more complex processes, such as bipolar
and BiCMOS. As an example, wafer yield is 90%, _defects per unit area_
is 2 per square centimeter, and die area is 1 square centimeter. Then die
yield is 90% * (1 + (2 * 1)/2.0)^{-2.0} or 22.5 %.
The bottom line is the number of good dies per wafer, which comes from
multiplying dies per wafer by die yield. The examples above predict
138*.225 or 31 good 1 cm-square dies per 15 cm wafer. As mentioned above,
both dies per wafer and die yield are sensitive to die size -- doubling
die area knocks die yield down to 10% and good chips per wafer to just
59*.10, or 6! Die size depends on the technology and gates required by
the function of the chip, but it is also limited by the number of pins
that can be placed on the border of a square die.
A 15-cm-diameter wafer processed in two-level metal CMOS costs a
semiconductor manufacturer about $550 in 1990 [fresh numbers, anybody?].
The cost for a 1-cm-square die with two defects per square cm on a 15-cm
wafer is $550/(138*.225) or $17.74.
What should a computer designer remember about chip costs? The
manufacturing process dictates the wafer cost, wafer yield, \alpha, and
defects per unit area, so sole control of the designer is die area. Since
\alpha is usually 2 or larger, die costs are proportional to the third
(or higher) power of the die area:
Cost of die = f (Die area^3)
The computer designer affects die size, and hence cost, both by what
functions are include on or excluded from the die an by the number of
I/O pins.
Cost of Testing Die and Cost of Packaging
Testing is the second term of the chip-cost equation, and the success
rate of testing (die yield) affects the costs of testing:
Cost of testing per hour * Average die test time
Cost of testing die = ---------------------------------------------------
Die yield
Since bad dies are discarded, die yield is in the denominator in the
equation -- the good must shoulder the costs of thesting those that fail.
Testing costs about $150 per hour in 1990 and die test take about 5 to 90
seconds on average, depending on the simplicity of the die and the
provisions to reduce testing time included in the chip. For example, a
$150 per hour and 5 seconds to test, the die test cost is $0.21. After
factoring in die yield for a 1-cm-square die, the costs are $0.93 per
good die. As in second example, let's assume testing takes 90 seconds.
The cost is $3.75 per untested die and $16.67 per good die. The bill so
far for our 1-cm-square die is $18.67 to $34.31, depending on how long it
takes to test. These two testing-time examples illustrate the importance
of reducing testing time in reducing costs.
Cost of Packaging and Final Die Yield
The cost of a package depends on the material used, the number of pins,
and the die area. The cost of the material used in the package is in part
determined by the ability to dissipate power generated by the die. For
example, a _plastic quad flat pack_ (PQFP) dissipating less than one
watt, with 208 of fewer pins, and containing a die up to one cm on a side
costs $3 in 1990. A ceramic _pin grid array_ (PGA) can handle 300 to 400
pins and a larger die with more power, but it costs $50. In addition to
the cost of the package itself is the cost of the labor to place a die in
the package and the bond the pads to the pins. We can assume that costs
$2. Burn-in exercises the packaged die under power for a short time to
catch chips that would fail early. Burn-in costs about $0.25 in 1990
dollars.
We are not finished with costs until we have figured in failure of some
chips during assembly and burn-in. Using the estimate of 90% for final
test yield, the successful must again pay for the cost of those that
fail, so our costs are $26.58 to $96.29 for the 1-cm-square die.
While those specific costs estimates may not hold, the underlying models
will. [...] shows dies per wafer, die yield, and their product against
the die are for a typical fabrication line, this time using programs that
more accurately predict die per wafer and die yield. [...] plots the
change in in area and cost as one dimension of a square die changes.
Changes to small dies make little cost differences, while 30% increases
to die size can double costs. The wise silicon designer will minimize die
area, testing time, and pins per chip and understand the costs of
projected packaging options when considering using more power, pins, or
area for higher performance.
Cost of a Workstation
To put the costs of silicon in perspective, [...] shows the approximate
costs of components in a 1990 workstation. Costs of a component can be
halved going from low volume to high volume; here we assume high-volume
purchasing of 100 000 units. While costs for units like DRAMs will surely
drop over time from those in [...], units whose prices have already been
cut, like displays and cabinets, will change very little.
The processor, floating-point unit, memory-management unit, and cache are
only 12% to 21% of the cost of the CPU board in [...]. Depending on the
options included in that system -- number of disks, color monitor, and so
on -- the processor components drop to 9 % and 16 % of the cost of a
system, as [...] illustrates. In the future two questions will be
interesting to consider: What costs can an engineer control? And what
costs can a computer engineer control?
Cost Versus Price -- Why They Differ and by How Much
[ Ask InTeL that one -- 'gene ]
ciao,
'gene
P.S. Linux: Where do you want to go tomorrow?
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