From: William Kitchen (bill@iglobal.net)
Date: Fri Feb 11 2000 - 15:57:17 MST
> If you're going by straight clock, normal SiGe should have a hard
> limit at ~150 GHz, or so. One would have to drastically simplify the
> CPU core before, of course. These gate delays add up too much.
TI is projecting DSP chips capable of three trillion
instructions/second by 2010. I'm not sure if that will be
achieved by pure sequential clock speed or by other tricks, but
either way it will be pretty impressive if they can really
accomplish it.
http://www.ti.com/sc/docs/news/1999/99086.htm
---
Peace,
William Kitchen
The future is ours to create.
This archive was generated by hypermail 2.1.5 : Fri Nov 01 2002 - 15:26:45 MST