5I20 PCI BRIDGE INTERFACE/MISC CONNECTIONS

BRIDGE CONNECTIONS:

SIGNAL NAME		IC PIN 		FUNCTION		

LAD0			153		LOCAL AD BUS		
LAD1			146		""
LAD2			142		""
LAD3			135		""
LAD4			126		""
LAD5			119		""
LAD6			115		""
LAD7			108		""
LAD8			174		""
LAD9			173		""
LAD10			172		""
LAD11			168		""
LAD12			167		""
LAD13			166		""
LAD14			165		""
LAD15			164		""
LAD16			163		""
LAD17			162		""
LAD18			152		""
LAD19			151		""
LAD20			150		""
LAD21			149		""
LAD22			148		""
LAD23			147		""
LAD24			141		""
LAD25			140		""
LAD26			139		""
LAD27			138		""
LAD28			136		""
LAD29			134		""
LAD30			133		""
LAD31			132		""

LA2			129		LOCAL NON MUXED ADDRESS BUS
LA3			127		""
LA4			125		""
LA5			123		""
LA6			122		""
LA7			121		""
LA8			120		""
		
/BHE0			175		LOCAL BYTE ENABLE 0
/BHE1			176		LOCAL BYTE ENABLE 1
/BHE2			178		LOCAL BYTE ENABLE 2
/BHE3			179		LOCAL BYTE ENABLE 3
			
ALE			97		LOCAL ADDRESS LATCH ENABLE
/ADS			98		LOCAL ADDRESS STROBE					
/BLAST			99		LAST TRANSFER OF BURST (FROM BRIDGE)					
/BTERM			109		BURST TERMINATE SIGNAL (FROM FPGA)
/LRD			100		LOCAL READ STROBE	
/LWR			160		LOCAL WRITE STROBE (AND CONFIG CS)
LW/R			101		LOCAL TRANSFER DIRECTION: LOW=READ
READY			102		BRIDGE READY INPUT
INT1			112		FPGA IRQ SIGNAL TO BRIDGE
WAITO			113		BRIDGE WAIT STATE INDICATOR OUT	
LOCKO			114		BRIDGE LOCKED TRANSFER INDICATOR OUT
FPGACS0			110		FPGA CHIP SELECT 0
FPGACS1			111		FPGA CHIP SELECT 1

GCLK0			80		IOCLK = IO0
GCLK1			77		IOCLK = I048
GCLK2			182		33 MHZ LOCAL BUS = PCI CLK
GCLK3			185		50 MHZ XTAL