Phil Blake wrote:
> I was reading that the P4 running at 2GHz actually got as much done
> as the P3 running at 1GHz.
>
> Is Moores Law just based on the speed of the clock or does it tie in
> with performance?
Below are some excerpts from a note I sent my brother in response
to his comment on the same news item (including references).
> The 3-atom gate thickness sounds too thin. Bell Labs showed
> that < ~10 atoms you can't reproduce things reliably enough.
> You get punch through and tunneling which drives up leakage
> that causes your chip to run hotter.
>
> Now, I what I thought was news was this:
>
> > *New transistor could keep computer evolution on track. Engineers have new
> > information contradicting the most dire predictions about the imminent
> > demise of Moore's Law, a general rule that is central to the evolution and
> > success of the computer industry. Research findings to be presented in
> > December show how the rule might be kept in force for another 25 years or
> > longer. (Eurekalert 12/6/00)
> > http://www.eurekalert.org/releases/pu-ntc120800.html
> > Nano Hub: www.nanohub.purdue.edu
> [This was from Gina's news via the transhumantech list I think]
>
> I think they may be modeling the vertical transistors that the group
> at Berkeley came up with last year. If you tip all the transistors
> on their side, that is going to give you a lot.
>
> If you take a look at:
> http://www.nec.co.jp/english/today/newsrel/0012/0701.html
> That is a cool piece of technology because it works in 3D.
> However, you note they claim: "2,750 nanometers (nm)" which
> is really 2.7 microns, which is 15 times larger than current
> chip line widths (0.18 microns). So nanotech is now the rage
> and everything will be quoted in nm even when it could better
> be quoted in microns (for comparison purposes).
>
> Much better sources for information on the P4 include:
> http://www.it.fairfax.com.au/breaking/20001211/A271-2000Dec11.html
> (the Australians don't botch the units conversion as the Forbes
> online article does...)
> and
> http://www.anandtech.com/showdoc.html?i=1379
> which has much more technical detail.
>
> The Anandtech article says they are planning on using EUVL
> and 157nm deep UV lithography to implement the 30nm gate lengths
> by 2005. If accurate, that *would* be a significant breakthrough
> as I haven't seen anything indicating there would be production
> EUVL equipment available that soon. However, you have to
> remember this is *Intel* we are talking about and I'm fairly
> sure the Itanium is more than a year late...
>
...
> Also notice the fine print in one of the articles
> "...Intel focusing on voice and face recognition...".
> They are having a very hard time finding uses for the speed.
Some additional comments:
Technical overview of the Itanium is here:
http://www.sharkyextreme.com/hardware/guides/itanium/
and
http://www1.anandtech.com/showdoc.html?i=1175
and the slashdot discussion:
http://slashdot.org/article.pl?sid=00/12/04/0442206
The migration from the P III (which is really a Pentium Pro)
to the P4 is doubling the number of pipline stages which
allows them to increase the clock speed. I'm a bit fuzzy
on why more stages is better. It may have to do with being
able to make the operations each stage does "simpler" and
therefore smaller on the chip, therefore reducing propagation
delay limits. One of the problems with simply increasing
chip speed is that it makes the processors consume more power,
thus running hotter and shortening their life. Intel is betting
on the fact that "speed" sells, not benchmarks. Because the P4
is going to move from a 0.18 micron process to 0.13 microns you
can lower the voltage (reducing power consumption) and still run the
chip faster. Moving to the smaller process lets Intel produce
more chips per wafer which increases profit.
The real advantages to the P4 will show up when you run them
on motherboards and memory that have higher data rates. Right
now many operations are memory bandwidth constrained, so the
P4s will tend to look poor in benchmarks even though they
are running at higher speeds. { Read -- when you are buying
systems go for the system with the highest bus speed. }
The Itanium helps somewhat because it has a much more parallel
internal architecture. It simply has more of everything.
The Itanium will not perform well without a *very* good
compiler. Intel is moving as much of the the instruction scheduling
and interference checking that is done on the chip in architectures
like the Alpha and current Pentium's out to the compile stage.
To make your programs run really fast, Itaniums may be performing
both the "then" and "else" clauses of an "if-then-else" statement
and then throw one result away when it gets the results of
evaluating the "if" conditional. That is a recipe for really
wasting energy though you will get your results sooner.
Ultimately the current architectures are doomed but they are
unlikely to change soon. A radical shift to processor-in-memory
architectures is required to eliminate the processor-memory
bandwidth limit. That could be solved by optical motherboard
interconnects (remember my slide from Extro III?) or by a radical
shift in processor/memory architectures, something IBM is doing
with Blue Gene for example. The problem is that new architectures
will probably require new programming paradigms because current
languages and programmers don't adapt well to massively parallel
processor-in-memory systems.
Actually, if the Intel announcements prove to be more than vapor-press,
and they really can implement a 0.07 micron (70 nm) with 30 nm gates
process by 2005 they will be accelerating up Moore's Law by 5-8 years
over the 1997 SIA Roadmap! See:
http://www.aeiveos.com/~bradbury/petaflops/siardmap.html
Its going to be really interesting to see the next version of the
SIA Roadmap to see if the industry consensus matches the Intel
Press department.
Robert
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