http://www.slashdot.org/comments.pl?sid=99/02/10/0852241&cid=361
The performance specs are bogus (Score:1)
by substrate on Wednesday February 10, @09:38AM
(User Info)
Look carefully (and subjectively, how rarely that happens) at the
performance specifications. The IBM Pacific Blue did 1.2 TeraOps
sustained peak running the actual ASCI codes (albeit in their own labs,
SGI beat those numbers and did it on site). The SBS HAL-4rW1 did 12.8
TeraOPs doing a sequence of 4 bit additions, or 3.8 TeraOPs on a 16 bit
adder.
This means that the memory and I/O subsystems aren't even exercised. Nobody uses a 4 bit addition as a performance spec, not even Intel.
The actual product description is unbelievable as well. The largest Xilinx FPGA's might be capable of being configured to fully emulate a 16 bit microprocessor. I haven't worked with them in a long time but when I worked with the 4000 series I figured I could shoehorn a rudimentary 8 bit processor into the largest devices. (which would mean that a rudimentary 8 bit microprocessor was produced for over one thousand dollars incidently. It's a bit cheaper to buy a PIC from MicroChip)
They said that they reached these performace levels with 280 of the largest Xilinx FPGA's. My take on what they've done is cram as many 4 bit adders onto a single FPGA and replicate it 280 times. They then had them all execute in parallel and pretended that this made up a supercomputer.
Keep in mind that performance on an FPGA isn't stunning. We're talking on the order of 10 nanoseconds to do the 4 bit addition.
So... if they've even designed and built this thing (which I doubt) the specifications are a complete fabrication.
I haven't checked yet, but browse through Xilinx's web site. If they don't mention this wonder of reconfigurable computing then it doesn't exist.
--
sentience@pobox.com Eliezer S. Yudkowsky
http://pobox.com/~sentience/AI_design.temp.html
http://pobox.com/~sentience/sing_analysis.html
Disclaimer: Unless otherwise specified, I'm not telling you
everything I think I know.