Eugene Leitl wrote:
> Do you know how long on-the-fly-compression/expansion of the
> pattern takes?
Unfortunately, no, they don't seem to discuss that aspect of the system in
detail anywhere. One of my biggest concerns about the whole project is the
fact that they are so vague on these kinds of details - it makes me wonder
whether they really know how to scale this thing up to an adequate size.
> Unfortunately you have to address the overlapping parts of the
> simulation. Each volume blocks are coupled at the edges, hence not
> completely independant. Also, FPGAs are 2d, and their circuitry
> density is order of magnitude lower than an ASIC.
Yes. Again, I wish they would give more details. It looks to me like what
they've really done is used the FPGAs to build a virtual machine specialized
to run their CA. They run each module of the CA one clock tick at a time,
in round-robin fashion, so that the system can deal with signal propagation
from module #1 while module 2 is executing. That lets them run the CA s lot
faster than they could on a conventional machine, but not nearly as fast as
on a real hardware-level CA.
> Hopefully, before very long we will get real hardware CAs instead of
> FPGAs.
We can hope. Mind you, I'm not sure that speed is really the bottleneck
here. IMHO they're going to need a breakthrough in GA techniques just to
exploit the hardware they already have. Otherwise they'll get stuck trying
to manually write fitness functions for all 64,000 modules, which doesn't
strike me as a very promising approach.
Billy Brown
bbrown@transcient.com
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