From: Eugene Leitl (Eugene.Leitl@lrz.uni-muenchen.de)
Date: Wed Mar 27 2002 - 12:41:57 MST
-- Eugen* Leitl leitl
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---------- Forwarded message ----------
Date: Wed, 27 Mar 2002 12:42:34 -0600
From: Christoph Wasshuber <wasshub@ti.com>
Cc: Beowulf@beowulf.org
Subject: Re: Hardware Progress: $397 (fwd)
> AMD plans to be
> producing chips with 65nm feature size by 2006,
> which should lead to a 20x reduction in cost.
Who says that 65nm feature size (which means
in this case gate length) results in 20x cost
reduction.
Given that all processing tools for such a
technology are more expensive and the fact that
we are already today at ~100nm in production
there is hardly a 20x cost reduction possible.
The real are reduction is dependent on minimum
pitch which is a lot larger more like 300nm.
Going to 300mm wafers will reduce overall cost,
but this has nothing to do with minimum feature
size.
I would think a cost reduction by 2-5x maximum
in 2006.
Chris....
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