From: Eugene Leitl (Eugene.Leitl@lrz.uni-muenchen.de)
Date: Thu Jan 09 1997 - 08:07:10 MST
"A designer who attempts to build a large neural network on a single
chip faces a problems common to all integrated circuits. We list some
of the major problems here. The first is cross talk. Closely spaced
wires tend to act as little antennas and get their signals mixed together
even if they are not physically connected. A second is decreased operating
speed. At the very small separations found in the most densely packed
integrated circuits, inductances and capacitances between the various
circuit elements become so large that they greatly slow the rate of
travel of electrical signals. A third is that the time spent by an
electron in passing through some parts of highly miniaturized circuits
is not long enough for the electron to affect the circuit. A fourth
has to do with the microscopic distribution of the elements placed
into the silicon to give it the desired electrical characteristics.
On a macroscopic scale, these elements are randomly distributed; on a
microscopic scale, however, there is no way to ensure that they will
be distributed evenly enough to guarantee uniform electrical properties
to the silicon.
A fifth problem is electromigration. Electrons passing down the tiny
conductors bump the atoms and cause them to migrate slowly towards
the positive end of the wire. There are so few atoms in the tiny
interconnect wires of these circuits in the first place that even a
small rearrangement sometimes results in a break in the wire. Sixth,
there is the problem of off-chip interconnect delays. For a given
number of neurodes on each chip, the number of interchip connections
required increases directly as the number of the neurodes in the
network being implemented. For instance, a 1-million-neurode
network will require 1000 chips and 1000 sets of interconnecting
wires. The speed of operation of such a system will probably be
slower than if all neurodes were on the same chip because it takes
time for the electrical signals to move the distances between chips.
Finally, there is a serious difficulty arising from the number of the
pins we can physically attach to a chip. This makes it difficult to
get rapid input and output for large masses of data. It also causes
difficulty in building highly interconnected network structures from
multiple chips."
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